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| m68hc05 microcontrollers freescale.com mc68hc05l16 mc68hc705l16 data sheet mc68hc05l16 rev. 4.1 9/2005
blank mc68hc05l16 ? mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. ? freescale semiconductor, inc., 2005. all rights reserved. mc68hc05l16 mc68hc705l16 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.freescale.com/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) may, 2002 4.0 reformatted to add additional page references and correct world wide web address n/a september, 2005 4.1 updated to meet freescale identity guidelines. throughout revision history mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 4 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 chapter 2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 3 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 chapter 4 resets and interr upts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 chapter 5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 chapter 6 parallel input/output (i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 chapter 7 oscillators/cl ock distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 chapter 8 simple serial peri pheral interface (sspi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 chapter 9 timer system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 chapter 10 lcd driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 chapter 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 03 chapter 12 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 chapter 13 mechanical specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 chapter 14 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 appendix a mc68hc705l16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 list of chapters mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 6 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 mcu structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.2 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.2.1 crystal or ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 1.5.2.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.3 xosc1 and xosc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.3.1 crystal resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.3.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.5 port a (pa0?pa7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.6 port b (pb0?pb7/kwi0 ?kwi7 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.7 port c (pc0/sdi, pc1/sdo, pc2/sck, pc3/tcap, pc4/evi, pc5/evo, pc6/irq2 , and pc7/irq1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.8 port d (pd1?pd3/bp1?bp3 and pd4?pd7/fp34?fp27). . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.9 port e (pe0?pe7/fp38?fp35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.10 vlcd1, vlcd2, and vlcd3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.11 ndly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6.1 mode entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6.2 single-chip mode (scm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.3 self-check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 chapter 2 memory map 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 input/output and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.1 read/write bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.2 read-only bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.3 write-only bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.4 reserved bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.5 reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.6 option map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 summary of internal registers and i/o map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table of contents mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 8 freescale semiconductor 2.4 option map for i/o configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.1 resistor control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.2 resistor control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.3 open-drain output control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.4 open-drain output control register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.5 key wakeup input enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.6 mask option status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.6 self-check rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7 mask rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 chapter 3 central processor unit (cpu) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.7 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.8 arithmetic/logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 chapter 4 resets and interrupts 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.1 irq1 and irq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.2 key wakeup interrupt (kwi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.3 irq (kwi) software consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.4 timer 1 interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2.5 timer 2 interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2.6 sspi interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2.7 timebase interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 interrupt control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.4 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 chapter 5 low-power modes 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table of contents mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 9 chapter 6 parallel input/output (i/o) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.2.2 port a data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.2 port c data direction register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.5 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.5.2 port d mux register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.6.2 port e mux register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 7 oscillators/clock distributions 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.2 osc clock divider and por counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.3 system clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.4 osc and xosc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.4.1 osc on line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.4.2 xosc on line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.4.2.1 xosc with fosce = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.4.2.2 xosc with fosce = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.4.2.3 xosc with fosce = 0 and stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.4.2.4 stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 7.5 timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.5.1 lcdclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.5.2 stup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.5.3 tbi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.5.4 cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.5.5 timebase control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.5.6 timebase control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.5.7 miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 8 simple serial peripheral in terface (sspi) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.3 functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.4 internal block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.4.1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.4.2 spdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table of contents mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 10 freescale semiconductor 8.4.3 spcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.4.4 spsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.4.5 clkgen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.5.1 sspi data i/o (sdi and sdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 8.5.2 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.6.1 serial peripheral control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.6.2 serial peripheral status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.6.3 serial peripheral data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.7 port function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 chapter 9 timer system 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.2 timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.2.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.2.2 output compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.2.3 input capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.2.4 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.2.5 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.2.6 timer during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.2.7 timer during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.3 timer 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.3.1 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.3.2 timer status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.3.3 output compare register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.3.4 timer counter register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.3.5 timebase control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.3.6 timer input 2 (evi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.3.7 event output (evo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9.4 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 chapter 10 lcd driver 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.2 lcd waveform examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.3 backplane driver and port selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.4 frontplane driver and port selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.5 lcd control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.6 lcd data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table of contents mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 11 chapter 11 instruction set 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.2 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.2.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.2.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.2.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.2.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.2.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.2.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.2.7 indexed, 16-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.2.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.3 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.3.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.3.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.3.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.3.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.3.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.4 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 chapter 12 electrical specifications 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3 operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.6 5.0-volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.7 3.3-volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.8 2.7-volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.9 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 chapter 13 mechanical specifications 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.2 quad flat pack (qfp) ? case 841b-01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 chapter 14 ordering information 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 14.2 mcu ordering forms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 14.3 application program media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 14.4 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.5 rom verification units (rvus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.6 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table of contents mc68hc05l16 ? mc68hc705l16 data sheet, rev. 4.1 12 freescale semiconductor appendix a mc68hc705l16 a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 a.2 differences between mc68hc05l16 and mc68hc705l16 . . . . . . . . . . . . . . . . . . . . . . . . . . 131 a.3 mcu structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 a.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 a.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 a.6 programming voltage (v pp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 a.7 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 a.7.1 mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 a.7.2 single-chip mode (scm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 a.7.3 bootstrap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 a.8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 a.9 boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 a.10 eprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 a.10.1 programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 a.10.2 program control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 a.11 lcd 1/2 duty and 1/2 bias timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 a.12 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 a.12.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 a.12.2 operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1 a.12.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 a.13 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 a.13.1 eprom programming voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 a.13.2 5.0-volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 42 a.13.3 3.3-volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 43 a.13.4 3.3-volt and 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 44 a.14 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 13 chapter 1 general description 1.1 introduction the mc68hc05l16 is an 80-pin microcontroller unit (m cu) with highly sophisticated on-chip peripheral functions. the memory map includes 16 kbytes of us er rom and 512 bytes of ram. the mcu has five parallel ports: a, b, c, d, and e. the mc68hc05l16 includes a timebase circ uit, 8- and 16-bit timers, a computer operating properly (cop) watchdog timer, liquid crystal display (lcd) drivers, and a simple serial peripheral interface (sspi). 1.2 features features of the mc68hc05l16 mcu include: low-cost hc05 core 16,400 bytes of mask rom, including 16 bytes of user vectors and 512 bytes of on-chip ram 16 bidirectional input-output (i/o) lines eight input-only lines 15 output-only lines, including 8-bit key wakeup interrupts pullup resistors options open-drain outputs options two interrupt request (irq) inputs 16-bit timer with input capture and output compare (timer 1) 8-bit event counter/modulus clock divider (timer 2) simple serial peripheral interface (sspi) lcd drivers ? 1-to-4 backplane drivers x 27-to-39 frontplane drivers on-chip timebase circuits with co p watchdog timer and timebase interrupts dual oscillators and selectable system clock frequency power-saving stop mode and wait mode 80-pin quad flat pack (qfp) 1.3 mcu structure figure 1-1 shows the structure of the mc68hc05l16 mcu. general description mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 14 freescale semiconductor figure 1-1. block diagram note a line over a signal name indicates an active low signal. for example, reset is active low. pa0 pc5/evo pc6*/irq2 pc7*/irq1 pc0/sdi timebase internal cop cpu m68hc05 cpu alu cpu registers control self-check rom system system processor clock 496 bytes accumulator index register stack pointer program counter condition code reg 3 2 pa1 pa2 pa3 pa4 port a data a pa5 pa6 pa7 osc sel lcd drivers mask rom reset v dd osc1 osc2 v ss port b data b key wakeup pb0/kwi0 pb1/kwi1 pb2/kwi2 pb3/kwi3 pb6/kwi6 pb7/kwi7 pb5/kwi5 pb4/kwi4 pc1/sdo pc2/sck pc3/tcap pc4/evi port c data c spi timer2 fp0?pf26 port e fp36/pd6 bp0 bp2/pd2 bp1/pd1 fp35/pd7 fp37/pd5 fp38/pd4 bp3/pd3 fp28/pe6 fp34/pe0 fp32/pe2 fp33/pe1 fp27/pe7 fp29/pe5 fp30/pe4 fp31/pe3 port d vlcd3 vlcd2 vlcd1 div ndly** 16,384 bytes xosc xosc1 xosc2 sram 512 bytes * open drain only when output ** the ndly pin should be connected to v dd . + 16 bytes dir reg dir reg dir reg mask options mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 15 1.4 mask options the three mask options on the mc68hc05l16 are: 1. rstr: reset pin pullup resistor 2. oscr: osc feedback resistor 3. xoscr: xosc feedback/damping resistor see 2.4.6 mask option status register . 1.5 functional pin description the mc68hc05l16 is available in the 80-pin qfp. the pin assignment is shown in figure 1-2 . figure 1-2. pin assignment for single-chip mode 1 20 40 41 60 61 80 21 v dd fp28/pe6 fp29/pe5 fp30/pe4 fp31/pe3 fp32/pe2 fp33/pe1 fp34/pe0 fp35/pd7 fp36/pd6 fp37/pd5 fp38/pd4 vlcd3 vlcd2 vlcd1 v ss ndly** xosc1 xosc2 reset v ss fp7 fp6 fp5 fp4 fp3 fp2 fp1 fp0 bp0 bp1/pd1 bp2/pd2 bp3/pd3 v dd pc7*/irq1 pc6*/irq2 pc5/evo pc4/evi pc3/tcap pc2/sck fp27/pe7 fp26 fp25 fp24 fp23 fp22 fp21 fp20 fp19 fp18 fp17 fp16 fp15 fp14 fp13 fp12 fp11 fp10 fp9 fp8 osc1 osc2 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0/kwi0 pb1/kwi1 pb2/kwi2 pb3/kwi3 pb4/kwi4 pb5/kwi5 pb6/kwi6 pb7/kwi7 pc0/sdi pc1/sdo * open drain only when output ** the ndly pin should be connected to v dd . general description mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 16 freescale semiconductor table 1-1. pin configuration pin number scm, self-check i/o pin number scm, self-check i/o 23 24 25 26 27 28 29 30 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 i/o i/o i/o i/o i/o i/o i/o i/o 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 fp0 fp1 fp2 fp3 fp4 fp5 fp6 fp7 fp8 fp9 fp10 fp11 fp12 fp13 fp14 fp15 fp16 fp17 fp18 fp19 fp20 fp21 fp22 fp23 fp24 fp25 fp26 o o o o o o o o o o o o o o o o o o o o o o o o o o o 31 32 33 34 35 36 37 38 pb0/kwi0 pb1/kwi1 pb2/kwi2 pb3/kwi3 pb4/kwi4 pb5/kwi5 pb6/kwi6 pb7/kwi7 i i i i i i i i 39 40 41 42 43 44 45 46 pc0/sdi pc1/sdo pc2/sck pc3/tcap pc4/evi pc5/evo pc6*/irq2 pc7*/irq1 i/o i/o i/o i/o i/o i/o i i 17 ndly** i 47 1 60 16 21 22 18 19 v dd v dd v ss v ss osc1 osc2 xosc1 xosc2 i i o o i o i o 80 2 3 4 5 6 7 8 fp27/pe7 fp28/pe6 fp29/pe5 fp30/pe4 fp31/pe3 fp32/pe2 fp33/pe1 fp34/pe0 o o o o o o o o 15 14 13 48 49 50 51 vlcd1 vlcd2 vlcd3 bp3/pd3 bp2/pd2 bp1/pd1 bp0 i i i o o o o 9 10 11 12 fp35/pd7 fp36/pd6 fp37/pd5 fp38/pd4 o o o o * open drain only when output ** the ndly pin should be connected to v dd . functional pin description mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 17 1.5.1 v dd and v ss power is supplied to the mcu through v dd and v ss . v dd is the positive supply, and v ss is ground. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration cu rrent demands on the power supply. to prevent noise problems, special care should be taken to provi de good power supply bypassing at the mcu by using bypass capacitors with good high-freq uency characteristics that are posi tioned as close to the mcu as possible. bypassing requirements vary, dependi ng on how heavily the mcu pins are loaded. 1.5.2 osc1 and osc2 the osc1 and osc2 pins are the connections for the 2-pin on-chip oscillator. the osc1 and osc2 pins can accept: a crystal as shown in figure 1-3 (a) an external clock signal as shown in figure 1-3 (b) the frequency, f osc , of the oscillator or external clock source is divided by 64 to produce the internal operating frequency, f op , by default. 1.5.2.1 crystal or ceramic resonator the circuit in figure 1-3 (a) shows a typical 2-pin oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturer?s recommendations should be followed, as the crystal parameters determine the external component values requi red to provide maximum stability and reliable startup. the load capacitance values used in the oscill ator circuit design should include al l stray capacitances. the crystal and components should be mounted as close as poss ible to the pins for st artup stabilization and to minimize output distortion. an internal startup feedback resistor of r of between osc1 and osc2 may be selected as a mask option for mc68hc05l16. typical r of resistor value is 5.5 m ? . figure 1-3. oscillator connections mcu c o2 (a) crystal connections osc1 osc2 c o1 r of unconnected external clock (b) external clock source connection osc1 osc2 mcu 4 mhz (typ) mask options general description mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 18 freescale semiconductor 1.5.2.2 external clock an external clock from another cmos-compatible dev ice can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 1-3 . this configuration is possible regardless of how the oscillator is set up. 1.5.3 xosc1 and xosc2 the xosc1 and xosc2 pins are the connections for the 2-pin on-chip oscillator. the xosc1 and xosc2 pins can accept: a crystal as shown in figure 1-4 (a) an external clock signal as shown in figure 1-4 (b) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op , if selected by sys1?sys0 bits. when xosc is not used, the xosc1 pin must be connected to the reset pin to ensure proper initialization of the clock circuitry. xosc2 pin should remain unconnected. 1.5.3.1 crystal resonator the circuit in figure 1-4 (a) shows a typical 2-pin oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturer?s recommendations should be followed, as the crystal parameters determine the external component values requi red to provide maximum stability and reliable startup. the load capacitance values used in the oscill ator circuit design should include al l stray capacitances. the crystal and components should be mounted as close as poss ible to the pins for st artup stabilization and to minimize output distortion. an internal startup feedback resistor of r xof between xosc1 and xosc2 and a damping resistor of r xod in series to xosc2 may be selected as a mask option. typical r xof resistor value is 15 m ? , and r xod resistor value is 1 m ? . figure 1-4. oscillator connections mcu c xo2 (a) crystal connections xosc1 xosc2 c xo1 r xof unconnected external clock (b) external clock source connection xosc1 xosc2 mcu r xod 32.768 khz ( typ) mask options functional pin description mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 19 1.5.3.2 external clock an external clock from another cmos-compatible dev ice can be connected to the xosc1 input, with the xosc2 input not connected, as shown in figure 1-4 (b). this configuration is possible regardless of how the oscillator is set up. 1.5.4 reset this pin can be used as an input to reset the mcu to a known startup state by pulling it to the low state. when power is removed, the reset pin contains a steering diode to discharge any voltage on the pin to v dd . the reset pin contains an internal schmitt trigger to improve its noise imm unity as an input. an internal reset pin pullup resistor may be selected as a ma sk option. a typical pullup resistor value is 46 k ? . 1.5.5 port a (pa0?pa7) port a is an 8-bit i/o port. the state of any pin is so ftware programmable and all po rt a lines are configured as inputs during power-on or reset. port a outputs may be configured as open-drain outputs and connected to a pullup resistor by software option. 1.5.6 port b (pb0?pb7/kwi0 ?kwi7 ) port b is an 8-bit input-only port that shares its lines with the key wakeup interrupt (kwi) system. port b has a pullup option by software option. 1.5.7 port c (pc0/sdi, pc1/sd o, pc2/sck, pc3/tcap, pc4/evi, pc5/evo, pc6/irq2 , and pc7/irq1 ) port c is an 8-bit i/o port. the state of any pin is software programmable and all port c lines are configured as inputs during power-on or reset. all port c lines may connect to a pullup resistor by software option. bits pc0?pc2 are shared with the sspi subsystem and may be configured as open-drain outputs. bit 3 is shared with the tcap pin of timer 1 and may be configured as an open-drain output. bit 4 is shared with the evi bit of timer 2 and may be configured as an open-drain output. bit 5 is shared with the evo bit of timer 2 and may be configured as an open-drain output. bit 6 is shared with the irq2 input. this bit is an open-drain output-only pin configured as an output. bit 7 is shared with the irq1 input. this bit is an open-drain output-only pin configured as an output. 1.5.8 port d (pd1?pd3/ bp1?bp3 and pd4?pd7/fp34?fp27) port d is a 7-bit output-only port that shares its bits with the lcd backplane/frontplane drivers. port d lines are configured as lcd outputs during power-on or reset. pd1?pd3 and pd4?pd7 outputs may be configured as open-drain outputs by a software option. general description mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 20 freescale semiconductor 1.5.9 port e (pe0?pe7/fp38?fp35) port e is an 8-bit output-only port that shares its bits with lcd frontplane drivers. port e lines are configured as lcd outputs during power-on or reset. pe0?pe3 and pe4?pe7 outputs may be configured as open-drain outputs by a software option. 1.5.10 vlcd1, vlcd2, and vlcd3 these pins provide offset to the lcd driver bias for adjusting the contrast of the lcd. 1.5.11 ndly this pin is reserved for factory test and should be connected to v dd in single-chip mode (user mode). 1.6 modes of operation the mc68hc05l16 has two operating modes: single-chip mode (scm) self-check mode single-chip mode, also called user mode, allows ma ximum use of pins for on -chip peripheral functions. the self-check capability of mc68hc05l16 provides an internal check to determine if the device is functional. 1.6.1 mode entry mode entry is done at the rising edge of the reset pin. once the device enters one of the modes, the mode cannot be changed by software. only an external reset can change the mode. at the rising edge of the reset pin, the device latches the states of irq1 and irq2 and places itself in the specified mode. while the reset pin is low, all pins are co nfigured as single-chip mode. table 1-2 shows the states of irq1 and irq2 for each mode entry. high voltage v tst = 2 x v dd is required to select modes other than single-chip mode. table 1-2. mode select summary modes reset pc6/irq1 pc7/irq2 single-chip (user) mode v ss or v dd v ss or v dd self-check mode v tst v dd modes of operation mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 21 figure 1-5 . mode entry diagram 1.6.2 single-chip mode (scm) in this mode, all address and data bus ac tivity occurs within the mcu. t hus, no external pins are required for these functions. the single-chip mode allows the maximum number of i/o pins for on-chip peripheral functions, for example, ports a through e, and lcd drivers. 1.6.3 self-check mode in this mode, the reset vector is fetched from a 496-byte internal self-check rom at $fe00?$ffef. the self-check rom contains a self-check program to test the functions of internal modules. since this mode is not a normal user mode, all of the privileged control bits are accessible. this allows the self-check mode to be used for self- test of the device. v tst v dd v ss v dd v ss irq2 irq1 reset single-chip mode v tst = 2 x v dd v dd v ss general description mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 22 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 23 chapter 2 memory map 2.1 introduction the mc68hc05l16 contains a 16,384-byte mask rom, 496 bytes of self-check rom, and 512 bytes of ram. an additional 16 bytes of mask rom are provided for user vectors at $fff0?$ffff. the mcu?s memory map is shown in figure 2-1 . figure 2-1 . memory map 0000 0015 0016 0063 $0000 $000f $0010 $003f ram 512 bytes i/o registers i/o i/o 64 bytes $0000 $003f $0040 $00c0 $00ff $023f $0240 $0fff $1000 $4fff $5000 $fdff $fe00 $ffdf $ffe0 $ffef $fff0 $ffff unused mask rom unused self-check rom test vectors user vectors dual-mapped 16 bytes 0 63 64 191 192 255 256 575 576 4095 4096 20479 20480 65023 65024 65503 65504 65519 65520 65535 stack 64 bytes 48 bytes 16 kbytes 496 bytes memory map mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 24 freescale semiconductor 2.2 input/output and control registers the input/output (i/o) and control registers resi de in locations $0000?$003f. a summary of these registers is shown in figure 2-3 . the bit assignments for each register are shown in figure 2-4 . reading from unimplemented bits (denoted by shading) will retu rn unknown states (unless explicitly defined to read 0), and writing to unimplemented bits will have no effect. see also figure 2-2 . figure 2-2. register description key 2.2.1 read/write bits read/write bits are typically control bits. they are, in general, not modified by a module. reset indicates the initial value of the latch. 2.2.2 read-only bits read-only bits are status flag bits. they are indicato rs of module status. rese t indicates the value that will be read immediately after system reset or before the module is enabled. 2.2.3 write-only bits write-only bits are control bits. they typically return a state of 0 to prevent an inadvertent write to this bit by a read-modify-write instruction. reset indicate s the value that will be read immediately after system reset, which is the forced read value (typically 0). 2.2.4 reserved bits reserved bits are read-only bits that typically read 0. writes to these bits ar e ignored, and the user should not write 1 for future compatibility. reset indicates the value that will be read immediately after system reset which is the forced read value (typically 0). 2.2.5 reset value values specified on the row marked reset: are initial values of register bits after system reset. those bits unaffected by reset are marked with the letter u. those bits that are unaffected by reset but initialized by power-on reset are marked with an asterisk (*). $003e miscellaneous register (misc) read: ftup stup 0 0 sys1 sys0 fosce optm write: reset: * *001010 register address (main m ap unless otherwise specified) bit name (mnemonic) register name (full) register name (mnemonic) read write read-only bit read/write bit reset value summary of internal registers and i/o map mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 25 2.2.6 option map address locations $0000?$000f are dual mapped. when the optm bit in the misc register is cleared, the main address map is accessed. when the optm bi t in the misc register is set, the option address map is accessed. note although not necessary for this device, fo r future compatibility the optm bit should be cleared when accessing memory locations $0010 and above. 2.3 summary of internal registers and i/o map figure 2-3 contains a detailed memory map of the i/o registers. addr. register name bit 7654321bit 0 $0000 port a data register (porta) see page 52. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) see page 53. read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset $0002 port c data register (portc) see page 54. read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset $0003 port d data register (portd) see page 56. read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 1 write: reset:11111111 $0004 port e data register (porte) see page 57. read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset:11111111 $0005 reserved rrrrrrrr $0007 reserved rrrrrrrr $0008 interrupt control register (intcr) see page 45. read: irq1e irq2e 0 kwie irq1s irq2s 0 0 write: reset:00000000 $0009 interrupt status register (intsr) see page 46. read: irq1f irq2f 0 kwif 0 0 0 0 write: rirq1 rirq2 rkwif reset:00000000 $000a serial peripheral control register (spcr) see page 73. read: spie spe dord mstr 0 0 0 spr write: reset:00000000 = unimplemented r = reserved u = unaffected figure 2-3. main i/o map (sheet 1 of 5) memory map mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 26 freescale semiconductor $000b serial peripheral status register (spsr) see page 74. read:spifdcol000000 write: reset:00000000 $000c serial peripheral data register (sp- dr) see page 75. read: msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 lsb write: reset: unaffected by reset $000d reserved rrrrrrrr $000f reserved rrrrrrrr $0010 timebase control register 1 (tbcr1) see page 88. read: tbclk 0 lclk 0 0 0 t2r1 t2r0 write: reset:00000000 $0011 timebase control register 2 (tbcr2) see page 88. read: tbif tbie tbr1 tbr0 0 0 00 write: rtbif cope copc reset:00110000 $0012 timer control register (tcr) see page 80. read: icie oc1ie toie 0 0 0 iedg olvl write: reset:000000u0 $0013 timer status register (tsr) see page 81. read:icfoc1ftof00000 write: reset:uuu00000 $0014 input capture register high (ich) see page 80. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0015 input capture register low (icl) see page 80. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0016 output compare register 1 high (oc1h) see page 79. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0017 output compare register 1 low (oc1l) see page 79. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0018 timer counter register high (tcnth) see page 88. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-3. main i/o map (sheet 2 of 5) summary of internal registers and i/o map mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 27 $0019 timer counter register low (tcntl) see page 88. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $001a alternate timer counter register high (acnth) see page 79. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $001b alternate timer counter register low (acmtl) see page 79. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $001c timer control register 2 (tcr2) see page 85. read: ti2ie oc2ie 0 t2clk im2 il2 oe2 ol2 write: reset:00000000 $001d timer status register 2 (tsr2) see page 87. read: ti2f oc2f 00 00 00 write: rti2f roc2f reset:00000000 $001e output compare register 2 (oc2) see page 87. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $001f timer counter register 2 (tcnt2) see page 88. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000001 $0020 lcd control register (lcdcr) see page 100. read: lcde duty1 duty0 0 peh pel pdh 0 write: reset:00000000 $0021 lcd data register 1 (lcdr1) see page 101. read: f1b3 f1b2 f1b1 f1b0 f0b3 f0b2 f0b1 f0b0 write: reset: unaffected by reset $0022 lcd data register 2 (lcdr2) see page 101. read: f3b3 f3b2 f3b1 f3b0 f2b3 f2b2 f2b1 f2b0 write: reset: unaffected by reset $0023 lcd data register 3 (lcdr3) see page 101. read: f5b3 f5b2 f5b1 f5b0 f4b3 f4b2 f4b1 f4b0 write: reset: unaffected by reset $0024 lcd data register 4 (lcdr4) see page 101. read: f7b3 f7b2 f7b1 f7b0 f6b3 f6b2 f6b1 f6b0 write: reset: unaffected by reset addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-3. main i/o map (sheet 3 of 5) memory map mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 28 freescale semiconductor $0025 lcd data register 5 (lcdr5) see page 101. read: f9b3 f9b2 f9b1 f9b0 f8b3 f8b2 f8b1 f8b0 write: reset: unaffected by reset $0026 lcd data register 6 (lcdr6) see page 101. read: f11b3 f11b2 f11b1 f11b0 f10b3 f10b2 f10b1 f10b0 write: reset: unaffected by reset $0027 lcd data register 7 (lcdr7) see page 101. read: f13b3 f13b2 f13b1 f13b0 f12b3 f12b2 f12b1 f12b0 write: reset: unaffected by reset $0028 lcd data register 8 (lcdr8) see page 101. read: f15b3 f15b2 f15b1 f15b0 f14b3 f14b2 f14b1 f14b0 write: reset: unaffected by reset $0029 lcd data register 9 (lcdr9) see page 101. read: f17b3 f17b2 f17b1 f17b0 f16b3 f16b2 f16b1 f16b0 write: reset: unaffected by reset $002a lcd data register 10 (lcdr10) see page 101. read: f19b3 f19b2 f19b1 f19b0 f18b3 f18b2 f18b1 f18b0 write: reset: unaffected by reset $002b lcd data register 11 (lcdr11) see page 101. read: f21b3 f21b2 f21b1 f21b0 f20b3 f20b2 f20b1 f20b0 write: reset: unaffected by reset $002c lcd data register 12 (lcdr12) see page 101. read: f23b3 f23b2 f23b1 f23b0 f22b3 f22b2 f22b1 f22b0 write: reset: unaffected by reset $002d lcd data register 13 (lcdr13) see page 101. read: f25b3 f25b2 f25b1 f25b0 f24b3 f24b2 f24b1 f24b0 write: reset: unaffected by reset $002e lcd data register 14 (lcdr14) see page 101. read: f27b3 f27b2 f27b1 f27b0 f26b3 f26b2 f26b1 f26b0 write: reset: unaffected by reset $002f lcd data register 15 (lcdr15) see page 101. read: f29b3 f29b2 f29b1 f29b0 f28b3 f28b2 f28b1 f28b0 write: reset: unaffected by reset $0030 lcd data register 16 (lcdr16) see page 101. read: f31b3 f31b2 f31b1 f31b0 f30b3 f30b2 f30b1 f30b0 write: reset: unaffected by reset addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-3. main i/o map (sheet 4 of 5) option map for i/o configurations mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 29 2.4 option map for i/o configurations most of the i/o configurations are done in the option map ( figure 2-4 ). some options still remain as mask options for the mc68hc05l16 such as a pullup resistor for the reset pin and resistors for the osc1/osc2 and xosc1/xosc2 pins. these mask opti ons may be read by the mosr ($000f) in the option map. the option map is located at $0000?$000f of the main memory map and it is available when the optm bit in the misc register ($003e) is set. main re gisters at $0000?$000f are not available when optm = 1. i/o port data direction registers are contained in the option map in figure 2-4 . $0031 lcd data register 17 (lcdr17) see page 101. read: f33b3 f33b2 f33b1 f33b0 f32b3 f32b2 f32b1 f32b0 write: reset: unaffected by reset $0032 lcd data register 18 (lcdr18) see page 101. read: f35b3 f35b2 f35b1 f35b0 f34b3 f34b2 f34b1 f34b0 write: reset: unaffected by reset $0033 lcd data register 19 (lcdr19) see page 101. read: f37b3 f37b2 f37b1 f37b0 f36b3 f36b2 f36b1 f36b0 write: reset: unaffected by reset $0034 lcd data register 20 (lcdr20) see page 101. read: 0 0 0 0 f38b3 f38b2 f38b1 f38b0 write: reset: unaffected by reset $0035 reserved rrrrrrrr $003d reserved rrrrrrrr $003e miscellaneous register (misc) see page 67. read: ftup stup 0 0 sys1 sys0 fosce optm write: reset:* *001010 $003f reserved rrrrrrrr * unaffected by reset but initialized by power-on reset addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-3. main i/o map (sheet 5 of 5) memory map mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 30 freescale semiconductor addr. register name bit 7654321bit 0 $0000 port a data direction register (ddra) see page 52. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0001 reserved rrrrrrrr $0002 port c data direction register (ddrc) see page 55. read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0003 port d mux register (pdmux) see page 56. read: pdm7 pdm6 pdm5 pdm4 0 0 0 0 write: reset:00000000 $0004 port e mux register (pemux) see page 57. read: pem7 pem6 pem5 pem4 pem3 pem2 pem1 pem0 write: reset:00000000 $0005 reserved rrrrrrrr $0007 reserved rrrrrrrr $0008 resistor control register 1 (rcr1) see page 31. read: 0000rbhrblrahral write: reset:00000000 $0009 resistor control register 2 (rcr2) see page 31. read: rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 write: reset:00000000 $000a open-drain output control register 1 (wom1) see page 32. read: dwomh dwoml ewomh ewoml 0 0 awomh awoml write: reset:00000000 $000b open-drain output control register 2 (wom2) see page 32. read: 1 1 cwom5cwom4cwom3cwom2cwom1cwom0 write: reset:11000000 $000c reserved r rrrrrrr $000d reserved r rrrrrrr $000e key wakeup input enable register (kwien) see page 33. read: kwie7 kwie6 kwie5 kwie4 kwie3 kwie2 kwie1 kwie0 write: reset:00000000 $000f mask option status register (mosr) see page 33. read:rstroscrxoscr00000 write: reset:uuu00000 = unimplemented r = reserved u = unaffected figure 2-4. option map option map for i/o configurations mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 31 2.4.1 resistor c ontrol register 1 bits 7?4 ? reserved these bits are not used and always read as logic 0. rbh ? port b pullup resistor (h) when this bit is set, pullup resistors are connected to t he upper four bits of port b. this bit is cleared on reset. rbl ? port b pullup resistor (l) when this bit is set, pullup resistors are connected to the lower four bits of port b. this bit is cleared on reset. rah ? port a pullup resistor (h) when this bit is set, pullup resistors are connected to t he upper four bits of port a. this bit is cleared on reset. ral ? port a pullup resistor (l) when this bit is set, pullup resistors are connected to the lower four bits of port a. this bit is cleared on reset. 2.4.2 resistor c ontrol register 2 rc x ? port c pullup resistor (bit x ) when rc x bit is set, the pullup resistor is connected to the corresponding bit of port c. this bit is cleared on reset. address: option map ? $0008 bit 7654321bit 0 read: 0000rbhrblrahral write: reset:00000000 figure 2-5. resistor control register 1 (rcr1) address: option map ? $0009 bit 7654321bit 0 read: rc7 rc6 rc5 rc4 rc3 rc1 rc1 rc0 write: reset:00000000 figure 2-6. resistor control register 2 (rcr2) memory map mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 32 freescale semiconductor 2.4.3 open-drain output control register 1 dwomh ? port d open-drain mode (h) when this bit is set, the upper four bits of port d are configured as open-drai n outputs if these bits are selected as port d output by the pdh bit in the lcdcr. this bit is cleared on reset. dwoml ? port d open-drain mode (l) when this bit is set, the lower three bits of port d are configured as open-drain outputs if the corresponding bp x pin is not used by the lcd driver. this bit is cleared on reset. ewomh ? port e open-drain mode (h) when this bit is set, the upper four bits of port e (that are configured as i/o output by the peh bit in the lcdcr) are configured as open-drain outputs. this bit is cleared on reset. ewoml ? port e open-drain mode (l) when this bit is set, the lower four bits of port e (tha t are configured as i/o output by the pel bit in the lcdcr) are configured as open-drain out puts. this bit is cleared on reset. bits 3 and 2 ? reserved these bits are not used and always return to logic 0. awomh ? port a open-drain mode (h) when this bit is set, the upper four bits of port a that are configured as output (corresponding to the ddra bit set) become open-drain outpu ts. this bit is cleared on reset. awoml ? port e open-drain mode (l) when this bit is set, the lower four bits of port a that are configured as output (corresponding ddra bit set) become open-drain outputs. this bit is cleared on reset. 2.4.4 open-drain output control register 2 bits 7 and 6 ? reserved these bits are not used and always read as l ogic 1. when configured as output, pc6 and pc7 are always open drain. address: option map ? $000a bit 7654321bit 0 read: dwomh dwoml ewomh ewoml 0 0 awomh awoml write: reset:00000000 figure 2-7. open-drain output control register 1 (wom1) address: option map ? $000b bit 7654321bit 0 read: 1 1 cwom5 cwom4 cwom3 cwom2 cwom1 cwom0 write: reset:11000000 figure 2-8. open-drain output control register 2 (wom2) option map for i/o configurations mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 33 cwom x ? port c open-drain mode (bit x ) when cwom x bit is set, port c bits x are configured as open-drain outputs if ddrc x is set. this bit is cleared on reset. 2.4.5 key wakeup input enable register kwie x ? key wakeup input enable (bit x ) when kwie x bit is set, the kwi x (pb x ) input is enabled for key wakeup interrupt. this bit is cleared on reset. 2.4.6 mask option st atus register the mask option status register (mosr) indicates t he state of mask options specified prior to production of the mc68hc05l16. rstr ? reset pin pullup resistor when this bit is set, it indicates an inter nal pullup resistor is attached to the reset pin by mask option. oscr ? osc feedback resistor when this bit is set, it indicates that an internal feedback resistor is attached between osc1 and osc2 by mask option. xoscr ? osc feedback resistor when this bit is set, it indicates that an inter nal feedback resistor is attached between xosc1 and xosc2. the damping resistor at the xo sc2 pin is attached by mask option. bits 4?0 ? reserved these bits are not used and always read as logic 0. address: option map ? $000e bit 7654321bit 0 read: kwie7 kwie6 kwie5 kwie4 kwie3 kwie2 kwie1 kwie0 write: reset:00000000 figure 2-9. key wakeup input enable register (kwien) address: option map ? $000f bit 7654321bit 0 read:rstroscrxoscr00000 write: reset:uuu00000 = unimplemented u = unaffected figure 2-10. mask option status register (mosr) memory map mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 34 freescale semiconductor 2.5 ram the 512-byte internal ram is positioned at $0040?$023f in the memory map. the lower 192 bytes are positioned in the page zero which are accessible by the direct addressing mode. the upper 64 bytes of this area (page zero) are used for the cpu stack. care should be taken if the stack area is used for data storage. the remaining 320 bytes of ram, $0100?$023f , are accessed by ex tended addressing mode. the ram is implemented with static cells and re tains its contents during the stop and wait modes. 2.6 self-check rom self-check rom is 496 bytes of mask rom positioned at $fe00?$ffef. this rom contains self-check programs and reset/interrupt vectors in the self-check mode. 2.7 mask rom the 16,384-byte user rom is positioned at $1000?$4fff, and an additional 16 bytes of rom are located at $fff0?$ffff for user vectors. mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 35 chapter 3 central processor unit (cpu) 3.1 introduction this section describes the central processor unit (cpu). 3.2 cpu registers the mcu contains five registers as shown in figure 3-1 . the interrupt stacking order is shown in figure 3-2 . figure 3-1. programming model figure 3-2. stacking order a 70 x 70 hinzc ccr 11 sp 70 pc 15 0 accumulator index register program counter stack pointer condition code 0 0 0 0 0 15 0 0 0 register index register pcl accumulator condition code pch 111 70 stack i n t e r r u p t decreasing unstack r e t u r n increasing note: since the stack pointer decrements during pushes, the pcl is stacked first, followed by pch, etc. pulling from the stack is in the reverse order. memory addresses memory addresses register central processor unit (cpu) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 36 freescale semiconductor 3.3 accumulator the accumulator (a) is a general-purpose, 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.4 index register the index register (x) is an 8-bit register used fo r the indexed addressing value to create an effective address. the index register may also be used as a temporary storage area. 3.5 condition code register the condition code register (ccr) is a 5-bit register in which the h, n, z, and c bits are used to indicate the results of the instruction just executed, and the i bi t is used to enable or disable interrupts. these bits can be tested individually by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. interrupt (i) when this bit is set, the timer and external interrupt are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the i bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the la st arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is a ffected also during bit test and branch instructions and during shifts and rotates. 70 a 70 x ccr hinzc stack pointer mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 37 3.6 stack pointer the stack pointer (sp) contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stac k and incremented as data is pulled from the stack. when accessing memory, the 10 most significant bits are permanently set to 0000000011. these eight 0 bits are appended to the six least significant register bi ts to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and looses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 3.7 program counter the program counter (pc) is a 16-bit register that contains the address of the next byte to be fetched. 3.8 arithmetic/logic unit the arithmetic/logic unit (alu) performs the arithmetic and logical operations defined by the instruction set. the binary arithmetic circuits decode instructions and set up the alu for the selected operation. most binary arithmetic is based on the addition algorithm , carrying out subtraction as negative addition. multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the alu. the multiply instruction (mul) requires 11 in ternal processor cycles to complete this chain of operations. 15 7 0 0000000011 sp 15 0 pc central processor unit (cpu) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 38 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 39 chapter 4 resets and interrupts 4.1 introduction in user operating modes, the reset/interrupt vect ors are located at the top of the address space ($fff0?$ffff). in self-check mode, the reset/interrupt vectors are located at $ffe0?$ffef in the internal self-check rom. descriptions in this section assume a user operating mode is in use. table 4-1 shows the address assignments for the vectors. upon reset, the i bit in the condition code register is set and interrupts are disabled (masked). when an interrupt occurs, the i bit is set automatically by har dware after stacking the condition code register (ccr). all interrupts in the mc68hc05l16 follow a fixed hardware priority circuit to resolve simultaneous requests. each interrupt has a software programmable interrupt mask bit which may be used to selectively inhibit automatic hardware res ponse. in addition, the i bit in the ccr acts as a class inhibit mask to inhibit all sources in the i-bit class. reset and software interrupt (swi) are not masked by the i bit in the ccr. swi is an instruction rather than a prioritized asynchronous interrupt source. in a sense, it is lower in priority than any source because once any inte rrupt sequence has begun, swi cannot override it. in another sense, it is higher in priority than any hardware sources, except reset, because once the swi opcode is fetched, no other sources can be honored until after the first instruction in the swi service routine has been executed. swi causes the i mask bit in the ccr to be set. table 4-1. interrupt vector assignments vector address interrupt source masked by local mask priority (1 = highest) fff0?fff1 timebase i bit tbie 7 fff2?fff3 sspi i bit spie 6 fff4?fff5 timer 2 ti2i oc2i i bit i bit ti2ie oc2ie 5 5 fff6?fff7 timer 1 ici oc1i toi i bit i bit i bit icie oc1ie toie 4 4 4 fff8?fff9 kwi i bit kwie 3 fffa?fffb irq irq1 irq2 i bit i bit irq1e irq2e 2 2 fffc?fffd swi none none same level as an instruction fffe?ffff reset cop reset pin power-on none none none cope none none 1 1 1 resets and interrupts mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 40 freescale semiconductor 4.2 interrupts there are six hardware interrupt sources in the mc68hc05l16: irq1 and irq2 key wakeup interrupt (kwi ) timer 1 (toi, ici, and oc1i) timer 2 (ti2i and oc2i) serial transfer complete interrupt (sspi) timebase interrupt (tbi) 4.2.1 irq1 and irq2 two external interrupt request inputs, irq1 and irq2 , share the same vector address at $fffa and $fffb. bits irq1s and irq2s in interrupt control register (intcr) control whether irq1 and irq2 , respectively, respond only to the falling edge or falling edge and low level to trigger an interrupt. the irq1 and irq2 are enabled by irq1e and irq2e bits and irq1f and ir q2f bits are provided as an indicator in the interrupt status register (intsr). since the irq1(2)f can be set by either the pins or the data latches of pc7(6), be sure to clear the flags by software before setting the irq1(2)e bit. the irq1 and the irq2 pins are shared with port c bit 7 and bit 6, respectively, and irq x pin states can be determined by reading port c pins. the bil and bih instructions apply only to the irq1 input. 4.2.2 key wakeup interrupt (kwi ) eight key wakeup inputs (kwi0 ?kwi7 ) share pins with port b. each key wakeup input is enabled by the corresponding bit in the kwien register which resides in the option map, and kwi is enabled by the kwie bit in the intcr. when a falling edge is detected at one of the enabled key wakeup inputs, the kwif bit in the intsr is set and kwi is generated if kwie = 1. each input has a latch which responds only to the falling edge at the pin, and all input latches are cleared at the same time by clearing the kwif bit. see figure 4-6 . 4.2.3 irq (kwi) software consideration irq and kwi interrupts have a timing delay in a case described in figure 4-2 . this section shows programming for proper interrupts with irq or kwi . figure 4-1 shows an example of timer1 interrupt. in this case, the interrupt by tof occurs as soon as the toie (timer1 overflow interrupt enable) bit is set. figure 4-1. timer 1 interrupt cli bset toie, tcr lda #$55 . . . . . tof interrupt pending interrupt occurs before this instruction interrupts mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 41 figure 4-2 shows an example of irq1 interrupt. in this case , the interrupt occurs after execution the instruction following the instruction which sets irq1e bit. the similar action occurs against irq2 and kwi interrupts. figure 4-2. irq timing delay this problem can be solved by using a software patch like figure 4-3 . a similar procedure could be used for irq2 or kwi . figure 4-3. software patch for irq1 4.2.4 timer 1 interrupt three timer 1 interrupts (toi, ici, and oc1i) share the same interrupt vector at $fff6 and $fff7. see 9.2 timer 1 . 4.2.5 timer 2 interrupt two timer 2 interrupts (ti2i and oc2i) share the same interrupt vector at $fff4 and $fff5. see 9.3.1 timer control register 2 . 4.2.6 sspi interrupt the sspi transfer complete interrupt uses the vector at $fff2 and $fff3. see chapter 8 simple serial peripheral interface (sspi) . 4.2.7 timebase interrupt the timebase interrupt uses the vector at $fff0 and $fff1. see 7.5 timebase . cli bset irq1e, intcr lda #$55 . . . . . interrupt occurs after this instruction irq1 interrupt pending cli bset irq1e, intcr nop lda #$55 . . . . interrupt occurs after this instruction irq1 interrupt pending resets and interrupts mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 42 freescale semiconductor figure 4-4. interrupt flowchart internal interrupt (1) irq external interrupt load pc from swi: $fffc?$fffd irq x : $fffa?$fffb kwi : $fff8?$fff9 timer 1: $fff6?$fff7 timer 2: $fff4?$fff5 sspi: $fff2?$fff3 tbi: $fff0?$fff1 set i bit in cc register stack pc, x, a, ccr clear irq request latch fetch next instruction execute instruction n n y y y n i bit in ccr set ? swi instruction ? n y rti instruction ? n y restore registers from stack: ccr, a, x, pc 1. kwi , timer 1, timer 2, sspi, and tbi from reset interrupts mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 43 figure 4-5. irq1 and irq2 block diagram d c h sel irq1s q irq1f read instruction for bih/bil d c h sel irq2s q irq2f read instruction data bus data bus reset/por irq1e irq2e w rite 1 to reset/por rite 1 to rirq1 int 0 1 1 0 q irq1 (pc7) irq2 (pc6) r s r r s q r resets and interrupts mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 44 freescale semiconductor figure 4-6. key wakeup interrupt (kwi ) kwie1 d c q h read kwif kwie0 q kwif d c q h d c q h kwie7 reset/por data bus kwi2 to kwi6 w rite 1 to rkwif kwie kwi0 (pb0) kwi1 (pb1) kwi7 (pb7) r r r s r kwi interrupt control register mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 45 4.3 interrupt control register irq1e ? irq1 interrupt enable the irq1e bit enables irq1 interrupt when irq1f is set. this bit is cleared on reset. 0 = irq1 interrupt disabled 1 = irq1 interrupt enabled irq2e ? irq2 interrupt enable the irq2e bit enables irq2 interrupt when irq2f is set. this bit is cleared on reset. 0 = irq2 interrupt disabled 1 = irq2 interrupt enabled bit 5 ? reserved this bit is not used and is always read as logic 0. kwie ? key wakeup interrupt (kwi) enable the kwie bit enables key wakeup interrupt when kwif is set. this bit is cleared on reset. 0 = kwi disabled 1 = kwi enabled irq1s ? irq1 select edge sensitive only 0 = irq1 configured for low level and negative edge sensitive 1 = irq1 configured to re spond only to negative edges irq2s ? irq2 select edge sensitive only 0 = irq2 configured for low level and negative edge sensitive 1 = irq2 configured to re spond only to negative edges bits 1 and 0 ? reserved these bits are not used and always read as logic 0. address: $0008 bit 7654321bit 0 read: irq1e irq2e 0 kwie irq1s irq2s 0 0 write: reset:00000000 figure 4-7. interrupt control register (intcr) resets and interrupts mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 46 freescale semiconductor 4.4 interrupt status register irq1f ? irq1 interrupt flag when irq1s = 0, the falling edge or low level at the irq1 pin sets irq1f. when irq1s = 1, only the falling edge sets the irq1f bit. if the irq1e bit and this bit are set, an interrupt is generated. this read-only bit is cleared by wr iting a logic 1 to the rirq1 bit. reset clears this bit. irq2f ? irq2 interrupt flag when irq2s = 0, the falling edge or low level at the irq2 pin sets irq2f. when irq2s = 1, only the falling edge sets the irq2f bit. if the irq2e bit and this bit are set, an interrupt is generated. this read-only bit is cleared by wr iting a logic 1 to the rirq2 bit. reset clears this bit. bit 5 ? reserved this bit is not used and is always read as logic 0. kwif ? key wakeup interrupt flag when the kwie x bit in the kwien register is set, the falling edge at the kwi x pin sets the kwif bit. if the kwie bit and this bit are set, an interrupt is generated. this read-only bit is cleared by writing a logic 1 to the rkwif bit. reset clears this bit. rirq1 ? reset irq1 flag the rirq1 bit is a write-only bit and is always read as logic 0. writing a logic 1 to this bit clears the irq1f bit and writing logic 0 to this bit has no effect. rirq2 ? reset irq2 flag the rirq2 bit is a write-only bit and is always read as logic 0. writing a logic 1 to this bit clears the irq2f bit and writing a logic 0 to this bit has no effect. bit 1 ? reserved this bit is not used and is always read as logic 0. rkwif ? reset kwi flag the rkwif bit is a write-only bit and is always read as logic 0. writing a logic 1 to this bit clears the kwif bit and writing a logic 0 to this bit has no effect. address: $0009 bit 7654321bit 0 read: irq1f irq2f 0 kwif 0 0 0 0 write: rirq1 rirq2 rkwif reset:00000000 = unimplemented figure 4-8. interrupt status register (intsr) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 47 chapter 5 low-power modes 5.1 introduction the mcu has two power-saving m odes, stop and wait. flowcharts of these modes are shown in figure 5-2 . 5.2 stop mode the stop instruction places the mcu in its lowest-power mode. in stop mode, the internal main oscillator osc is turned off, halting all internal processing, in cluding timer operations (timer 1, timer 2, and computer operating properly (cop) watchdog timer). suboscillator xosc does not stop oscillating. therefore, if xosc is used as the clock source for the cop watchdog timer, cop is still functional in stop mode. see chapter 7 oscillators /clock distributions . during stop mode, the timer prescaler is cleared. the i bit in the condition code register (ccr) is cleared to enable external interrupts. all other registers an d memory remain unaltered. all input/output lines remain unchanged. the processor can be brought out of stop mode only by reset or an interrupt from irq1 , irq2 , kwi , sspi (slave mode only), or tbi. see chapter 7 oscillators/clock distributions . 5.3 wait mode the wait instruction places the mcu in a low-po wer mode, but wait mode consumes more power than stop mode. all cpu action is suspended, but on-chip peripherals and oscillators remain active. any interrupt or reset (including a cop reset) will cause the mcu to exit wait mode. during wait mode, the i bit in the ccr is cleared to enable interrupts. all other registers, memory, and input/output lines remain in their previous state. the timers may be enabled to allow a periodic exit from wait mode. wait mode must be exited and the cop must be reset to prevent a cop timeout. the reduction of power in wait mode depends on how many of the on-chip peripheral's clocks can be shut down. therefore, the amount of power that will be c onsumed is dependent on the application, and it would be prohibitive to test all parts for all vari ations. for these reasons, the values given in chapter 12 electrical specifications reflect typical application conditions a fter initial characterization of silicon. low-power modes mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 48 freescale semiconductor figure 5-1. clock state and stop recovery/power-on reset delay diagrams reset int state c cpu: run ph2: x1/64 x1: on x2: on state b cpu: run ph2: x1/4 x1: on x2: on state d cpu: run ph2: x2/2 x1: on x2: on state a cpu: run ph2: x1/2 x1: on x2: on state e cpu: run ph2: x2/2 x1: off x2: on x1en = 1 x1en = 0 state a state b state c stop state d state e delay power-on int int stop stop reset int notes: ph2 is at same frequency as internal processor clock e. x1 = osc x2 = xosc x1en = fosce low power high speed stop ? e ? d ? c ? b ? a reset wait mode mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 49 figure 5-2. stop/wait flowcharts 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine reset ? oscillator active timer clock active processor clocks stopped clear i bit restart processor clock stop oscillator osc and all clocks except xosc clear i bit y y y y n n n external interrupt irq ? y n kwi interrupt ? y n timer 2 interrupt ? y n sspi interrupt ? y n timebase interrupt ? external interrupt irq? reset ? y n timer 1 interrupt ? kwi interrupt ? n n n y y timebase interrupt ? ? sspi interrupt ? ? n y notes: ? slave mode only ? when tbclk = 0 stop wait 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine if fosc = 1 turn on oscillator osc wait for time low-power modes mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 50 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 51 chapter 6 parallel input/output (i/o) 6.1 introduction the mcu has five parallel ports: port a has eight i/o pins. port b has eight input/only pins. port c has eight i/o pins. port d has seven output-only pins. port e has eight output-only pins. most of these 39 i/o pins serve multiple purposes depending on the configurat ion of the mcu system. the configuration is in turn controlled by hardware m ode selection as well as internal control registers. figure 6-1. port i/o circuitry for one bit data direction register bit latched output data bit i/o pin input reg bit input i/o output internal hc05 connections parallel input/output (i/o) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 52 freescale semiconductor 6.2 port a port a is an 8-bit, bidirectional, general-purpose por t. the data direction of a port a pin is determined by its corresponding ddra bit. when a port a pin is programmed as an output by the corresponding ddra bit, data in the porta data register becomes output data to the pin. this dat a is returned when the porta register is read. open drain or cmos outputs are selected by awom h and awoml bits in the wom1 register. if the awomh bit is set, the p-channel dr ivers of bits 7?4 output buffers are disabled (open drain). if the awoml bit is set, the p-channel drivers of bits 3?0 output buffers are disabled (open drain). when a bit is programmed as inpu t by the corresponding ddra bit, the pin level is read by the cpu. port a has optional pullup resistors. when the rah bit or ral bit in the rcr1 is set, pullup resistors are attached to the upper four bits or lower four bits of port a pins, respectively. when a pin outputs a low level, the pullup resistor is disconnected regardless of the rah or ral bit state. 6.2.1 port a data register read anytime; returns pin level if ddr set to input; re turns output data latch if ddr set to output write anytime; data stored in an internal latch; drives pin only if ddr set for output reset becomes high-impedance input 6.2.2 port a data direction register read anytime when optm = 1 write anytime when optm = 1 reset cleared to $00; all general-purpose i/o configured for input address: $0000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset figure 6-2. port a data register (porta) address: option map ? $0000 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 6-3. port a data direction register (ddra) port b mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 53 ddra x ? port a data direction register bit x 0 = configure i/o pin pa x to input 1 = configure i/o pin pa x to output 6.3 port b port b pins serve two basic functions: kwi input pins and general-purpose input pins. each kwi input is enabled or dis abled by the corresponding kwie x bit in the kwien register, and the usage of the kwi input does not affect the general-purpose input function. port b pin states may be read any time regardless of the configurations. since there is no output drive logic associated with port b, there is no ddrb register and the write to the portb register has no meaning. port b has optional pullup resistors. when the rbh or rbl bit in the rcr1 is set, pullup resistors are attached to the upper four bits or lower four bits of port a pins, respectively. read anytime; returns pin level write has no meaning or effect reset unaffected; always an input port 6.4 port c port c pins share functions with several on-chip peri pherals. a pin function is controlled by the enable bit of each associated peripheral. bit 7 and bit 6 of port c are general-purpose i/o pins and irq input pins. the ddrc7 and ddrc6 bits determine whether the pin states or the data latch states should be read by the cpu. since irq1f or irq2f can be set by either the pins or the data latc hes, when using irqs, be sure to clear the flags by software before enabling the irq1e or irq2e bits. when configured for output port, pc6 and pc7 are open drain only. when v dd output is required, a pullup resistor must be enabled. the pc5 pin is a general-purpose i/o pin and the direct ion of the pin is determined by the ddrc5 bit in the data direction register c (ddrc). when the event out put (evo) is enabled, th e pc5 is configured as an event output pin and the ddrc5 bit has meaning onl y for the read of pc5 bit in the portc register; if the ddrc5 is set, the pc5 data latch is read by the cpu. otherwise, pc5 pin level (evo state) is read. when evo is disabled, the ddrc5 bit decides the idling state of evo (if ddrc5 = 1). address: $0001 bit 7654321bit 0 read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset figure 6-4. port b data register (portb) parallel input/output (i/o) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 54 freescale semiconductor the pc4 and pc3 pins share functions with the time r input pins (evi and tcap). these bits are not affected by the usage of timer input functions and t he directions of pins are always controlled by the ddrc4 and ddrc3 bits. also, th e ddrc4 and ddrc3 bits determine whether the pin states or data latch states should be read by the cpu. note since the tcap pin is shared with the pc3 i/o pin, changing the state of the pc3 ddr or data register can cause an unwanted tcap interrupt. this can be handled by clearing the icie bi t before changing the configuration of pc3 and clearing any pending interrupts before enabling icie. since the evi pin is shared with the pc4 i/o pin, ddrc4 should always be cleared whenever evi is used. evi should not be used when ddrc4 is high. the pc2?pc0 pins are shared with the simple seri al peripheral interface (sspi). when the sspi is not used (spe = 0), ddrc2?ddrc0 bits control the directio n of the pins, and when the sspi is enabled, the pins are configured as serial clock output or input (s ck), serial data output (sdo), and serial data input (sdi). the direction of the sck depends on the mstr bit in the spcr. when portc is read, the value read will be determined by the data direction register. when the port is configured for input (ddrc2, ddrc1, or ddrc0 equal to logic 0) the pin state is read. when the port is configured for output (ddrc2, ddrc1, or ddrc0 equal to logic 0), the output data latch is read. port c has optional pullup resistors. when the rc x bit in the rcr2 is set, pullup resistors are attached to the pc x pin. when a pin outputs a low level, the pullup resistor is disconnected regardless of an rcr2 register bit being set bits 5?0 have open drain or cmos output options, which are controlled by the corresponding wom2 register bits. these open drain or cmos output opti ons may be selected for either the general-purpose output ports or the peripheral outputs (evo, sck, and sdo). 6.4.1 port c data register read anytime; returns pin level if ddr set to input; re turns output data latch if ddr set to output write anytime; data stored in an internal latch; drives pin only if ddr set for output writes do not change pin state when pin configured for sdo, sck, and evo peripheral output reset becomes high-impedance input address: $0002 bit 7654321bit 0 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset figure 6-5. port c data register (portc) port d mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 55 6.4.2 port c data direction register read anytime when optm = 1 write anytime when optm = 1 reset cleared to $00; all general-purpose i/o configured for input ddrc x ? port c data direction register bit x the timer and sspi force the i/o state to be an output for each port c line associated with an enabled output function such as sdo and evo. for these cases, the data direction bits will not change. 0 = configure i/o pin pc x to input 1 = configure i/o pin pc x to output 6.5 port d port d pins serve one of two basic functions depending on the mcu mode selected: lcd frontplane and backplane driver outputs general-purpose output pins since port d is an output-only port, there is no ddrd register. instead of ddrd, port d mux control register (pdmux) is used. bits 7?4 of this register control the port/lcd muxing of port d bits 7?4, respectively, on a bit-wide basis. these bits are cleared on reset, and writi ng a logic 1 to any bit will turn that pin into a port output. this function is supe rseded by the pdh bit in the lcd control register. when pdh is set, the upper four bits of port d become port outputs regardless of the state of the pdmux bits. on reset, all port d outputs are disconnected from the pins and the port d data latches are set to a logic 1. the pin connections of the lower three bits of port d depend on the lcd duty selection by the duty1 and duty0 bits in the lcdcr. when the lcd duty is not 1/ 4, the unused backplane drive r(s) is (are) replaced by the port d output pin(s) automatically. if dwomh bit or dwoml bit in the wom1 register is set, the p-channel drivers of output buffers at the upper four bits or lower three bits, respective ly, are disabled (open-drain mode). these open-drain controls do not apply to the pins which are conf igured as frontplane or backplane driver outputs. address: option map ? $0002 bit 7654321bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 figure 6-6. port c data direction register (ddrc) parallel input/output (i/o) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 56 freescale semiconductor 6.5.1 port d data register read anytime; returns output data latch; bit 0 is always read logic 1 write anytime (writes do not change pin stat e when configured for lcd driver output.) reset all bits set to logic 1 and output ports disc onnected from the pins (lcd is enabled on reset.) 6.5.2 port d mux register read anytime (when optm = 1, bits 3?0 always read logic 0.) write anytime (writes have no effect if pdh is set.) reset all bits cleared; lcd enabled pdm x ? port d mux control bit x 0 = configure pin pd x to lcd 1 = configure pin pd x to output 6.6 port e port e pins serve one of two basic f unctions depending on the mcu mode selected: lcd frontplane driver outputs general-purpose output pins since port e is an output-only port, there is no ddre register. instead of ddre, port e mux control register (pemux) is used. bits 7?0 of this regist er control the port/lcd muxing of port e bits 7?0 respectively on a bit-wide basis. these bits are clear ed on reset, and writing a logic 1 to any bit will turn that pin into a port output. this function is superse ded by the peh and pel bits in the lcd control register. when peh is set, the upper four bits of port e becom e port outputs regardless of the state of the pemux bits. likewise, when pel is set, the lower four bits of port e become outputs. address: $0003 bit 7654321bit 0 read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 1 write: reset:11111111 figure 6-7. port d data register (portd) address: option map ? $0003 bit 7654321bit 0 read: pdm7pdm6pdm5pdm40000 write: reset:00000000 figure 6-8. port d mux register (pdmux) port e mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 57 on reset, all port e outputs are disconnected from the pins and the port e data latches are set to logic 1. if ewomh bit or ewoml bit in the wom1 register is set, the p-channel driver of output buffers at the upper or lower four bits, respectively, are disabl ed (open-drain mode). these open-drain controls do not apply to the pins which are configured as frontplane driver outputs. 6.6.1 port e data register read anytime; returns output data latch write anytime (writes do not change pin stat e when configured for lcd driver output.) reset all bits set to logic 1 and output ports disc onnected from the pins (lcd is enabled on reset.) 6.6.2 port e mux register read anytime when optm = 1 write anytime (writes have no effect if peh/pel is set.) reset all bits cleared (lcd is enabled.) pem x ? port e mux control bit x 0 = configure pin pe x to lcd 1 = configure pin pe x to output address: $0004 bit 7654321bit 0 read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset:11111111 figure 6-9. port e data register (porte) address: option map ? $0004 bit 7654321bit 0 read: pem7 pem6 pem5 pem4 pem3 pem2 pem1 pem0 write: reset:00000000 figure 6-10. port e mux register (pemux) parallel input/output (i/o) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 58 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 59 chapter 7 oscillators/clock distributions 7.1 introduction there are two oscillator blocks: osc and xosc. several combinations of the clock distributions are allowed for the modules in the mc68hc05l16. refer to figure 7-1 . figure 7-1. clock signal distribution 7.2 osc clock divider and por counter the osc clock is divided by a 7-bit counter which is used for the system cloc k, timebase, and power-on reset (por) counter. clocks divided by 2, 4, and 64 are available for the system clock selections and a clock divided by 128 is provided fo r the timebase and por counter. the por counter is a 6-bit clock counter that is driven by the osc divided by 128. the overflow of this counter is used for setting ftup bit, releasin g the por, and resuming operation from stop mode. the 7-bit divider and por counter are in itialized to $0078 by two conditions: power-on detection when fosce bit is cleared 1/2 0 1/2 1 1/2 5 xosc1 xosc2 stop osc1 osc2 sys1 sys0 sel 1/2 osc divider 7-bit osc xosc clk ctrl por 6-bit timebase timer 2 timer 1 sspi cpu lcd driver and ports wait exclk 1/2 7 1/2 7 xclk fosce/ pwron system clock ftup oscillators/cloc k distributions mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 60 freescale semiconductor 7.3 system clock control the system clock is provided for all internal modules except timebase. both os c and xosc are available as the system clock source. the divide ratio is sele cted by the sys1 and sys0 bits in the misc register. (see table 7-1 .) by default, osc/64 is selected on reset. note do not switch the system clock to xosc (sys1 and sys0 = 11) when xosc clock is not available. the xo sc clock is available when stup flag is set. do not switch the system clock to osc (sys1 and sys0 = 00, 01, or 10) when osc clock is not available. t he osc clock is available when ftup flag is set. 7.4 osc and xosc the secondary oscillator (xosc) runs continuously after power up. the main oscillator (osc) can be stopped to conserve power via the stop instruction or the fosce bit in the misc register. the effects of restarting the osc will vary depending on the cu rrent state of the mcu, including sys0, sys1, and fosce. 7.4.1 osc on line if the system clock is osc, fosce should remain logic 1. executing the stop instruction in this condition will halt osc, put the mcu into a low-power mode, and clear the 6-bit por counter. the 7-bit divider is not initialized. exiting stop with external irq or reset re-starts the oscillator. when the por counter overflows, internal reset is released and execution can begin. the stabilization time will vary between 8064 and 8192 counts. note exiting stop with external reset will always return the mcu to the state as defined by the default register definitions, for example, sys0:sys1 = 1:0, fosce = 1. table 7-1. system bus clock frequency selection sys1 sys0 divide ratio cpu bus frequency (hz) osc = 4.0 m osc = 4.1943 m xosc = 32.768 k 00 osc 2 2.0 m 2.0972 m ? 01 osc 4 1.0 m 1.0486 m ? 10 osc 64 62.5 k 65.536 k ? 11 xosc 2 ? ? 16.384 k osc and xosc mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 61 figure 7-2. osc1, osc2, xosc1, and xosc2 mask options 7.4.2 xosc on line if xosc is the system clock (sys:sys1 = 1:1), osc can be stopped either by the stop instruction or by clearing the fosce bit. the suboscillator (xosc) never stops except duri ng power down. this clock also may be used as the clock source of the system clock and timebase. stup bit indicates that the xosc clock is available. osc and xosc pins have options for feedback and damping resistor implementations. these options are set through mask option and may be read through the mosr register. note when xosc is not used, the xosc1 input pin should be connected to the reset pin. figure 7-3. unused xosc1 pin 7.4.2.1 xosc with fosce = 1 if the system clock is xosc and fosce = 1, executi ng the stop instruction will halt osc, put the mcu into a low-power mode and clear the 6-bit por counter . the 7-bit divider is not initialized. exiting stop with external irq re-starts the oscillator; however , execution begins immedi ately using xosc. when the por counter overflows, ftup is set, signaling that osc is stable and osc can be used as the system clock. the stabilization time wi ll vary between 8064 and 8192 counts. r f r f r d xosc1 xosc2 xosc osc1 osc2 osc mask option mask option on chip off chip xosc1 xosc2 xosc reset logic on chip off chip no connect reset from external reset circuit oscillators/cloc k distributions mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 62 freescale semiconductor 7.4.2.2 xosc with fosce = 0 if xosc is the system clock, clearing fosce will stop osc and preset the 7-bit divider and 6-bit por counter to $0078. execution will continue with xo sc and when fosce is set again, osc will re-start. when the por counter overflows, ftup is set, signali ng that osc is stable and osc can be used as the system clock. the stabilization time will be 8072 counts. 7.4.2.3 xosc with fosce = 0 and stop if xosc is the system clock and fosce is cleared, further power reduction can be achieved by executing the stop instruction. in this case, osc is stopped, the 7-bit divider and 6-bit por counter are preset to $0078 (since fosce = 0) and execution is halted. exit ing stop with external irq does not re-start the osc; however, execution begins im mediately using xosc. osc may be re-started by setting fosce. when the por counter overflows, ftup will be set, si gnaling that osc is stable and can be used as the system clock. the stabilization time will be 8072 counts. 7.4.2.4 stop mode and wait mode during stop mode, the main oscillator (osc) is shut down and the clock path from the second oscillator (xosc) is disconnected. all modul es except timebase are halted. entering stop mode clears the ftup flag in the misc register and initializes the por counter. stop mode is exited by reset , irq1 , irq2 , kwi , sspi (slave mode), or timebase interrupt. if osc is selected as the system clock source during stop mode, cpu resumes after the overflow of the por counter and this overflow al so sets the ftup status flag. if xosc is selected as the system clock source durin g stop mode, no stop recovery time is required for exiting stop mode because xosc never stops. re-start of the main oscillator depends on the fosce bit. during wait mode, only the cpu clocks are halted and the peripheral modules are not affected. wait mode is exited by reset and any interrupts. table 7-2. recovery time requirements before reset or interrupt power-on reset external reset exit stop mode by interrupt cpu clock source stop fosce ???wait?? osc (osc on) out 1 ? no wait ? osc (osc off) out in in (1) 1. this case never occurs. 0 (2) 1 0 (1) 2. this case has no meaning for the applications. ? ? ? wait wait wait ? wait wait xosc (osc on) out 1 ? no wait ? xosc (osc off) out in in 0 1 0 ? ? ? wait wait wait ? no wait no wait timebase mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 63 7.5 timebase timebase is a 14-bit up-counter which is clocked by xosc input or osc input divided by 128. tbclk bit in the tbcr1 register selects the clock source. this 14-bit divider is initialized to $0078 only upon power-on reset (por). after counting 8072 clocks, the stup bit in the misc register is set. the divided clocks from the timebase are used for lcdclk, stup, tbi, and cop. (see figure 7-4 ). 7.5.1 lcdclk the clocks divided by 64 and 128 ar e used as lcd clocks at the lcd driver module, and clocks are selected by the lclk bit in the tbcr1. figure 7-4. timebase clock divider 7.5.2 stup timebase divider is initialized to $0078 by the pow er-on detection. when the count reaches 8072, the stup flag in the misc register is set. once the stup flag is set, it is never cleared until power down. 7.5.3 tbi timebase interrupts may be generated every 0.5, 0.25, 0.125, or 0.0039 seconds with a 32.768-khz crystal at xosc pins. the timebase interrupt flag (tbif) is set every period and interrupt is requested if the enable bit (tbie) is set. the clock divided by 128, 4096, 8192, or 16,384 is us ed to set tbif, and this clock is selected by the tbr1 and tbr0 bits in the tbcr2 register. (see table 7-3 .) sel 7-bit divider sel sel divide by 4 tbif tbclk lclk tbie 7-bit divider tbr1 tbr0 cop enable cop clear cop reset tbi lcd clock 1/2 6 1/2 7 1/2 0 1/2 5 1/2 6 1/2 7 xclk osc/2 7 0 1 0 1 oscillators/cloc k distributions mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 64 freescale semiconductor 7.5.4 cop the computer operating properly (cop) watchdog timer is controlled by the cope and copc bits in the tbcr2 register. the cop uses the same clock as tbi that is selected by the tbr1 and tbr0 bits. the tbi is divided by four and overflow of this divider generates cop time out reset if the cop enable (cope) bit is set. the cop timeout reset has the same vector address as por and external reset . to prevent the cop timeout, the cop divider is cleared by writ ing a logic1 to the cop clear (copc) bit. when the timebase divider is driven by the osc clock, clock for the divider is suspended during stop mode or when fosce is a logic 0. this may cause cop period stretching or no cop timeout reset when processing errors occur. to avoid these problems, it is recommended that the xosc clock be used for the cop functions. when the timebase (cop) divider is driven by the xosc clock, the divider does not stop counting and the copc bit must be triggered to prevent the cop timeout. table 7-3. timebase interrupt frequency tbcr2 divide ratio frequency (hz) tbr 1 tbr 0 osc = 4.0 m osc = 4.1943 m xosc = 32.768 k 00 tbclk 128 244 256 256 01tbclk 4096 7.63 8.00 8.00 10tbclk 8192 3.81 4.00 4.00 11tbclk 16,384 1.91 2.00 2.00 table 7-4. cop timeout period tbcr2 cop period (ms) tbr1 tbr0 osc = 4.0 mhz osc = 4.1943 mhz xosc = 32.768 khz min max min max min max 0 0 12.3 16.4 11.7 15.6 11.7 15.6 0 1 393 524 375 500 375 500 1 0 786 1048 750 1000 750 1000 1 1 1573 2097 1500 2000 1500 2000 timebase mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 65 7.5.5 timebase c ontrol register 1 read anytime write anytime (only one write is allowed on bit 7 after reset.) tbclk ? timebase clock the tbclk bit selects the timebase clock source. this bit is cleared on reset. after reset, write to this bit is allowed only once. 0 = xosc clock selected 1 = osc clock divided by 128 selected bit 6 ? reserved this bit is not used and always reads as logic 0. lclk ? lcd clock the lclk bit selects the clock for the lcd driver. this bit is cleared on reset. 0 = divide by 64 selected 1 = divide by 128 selected bits 4?2 ? reserved these bits are not used and always read as logic 0. t2r1 and t2r0 ? timer 2 prescale rate select bits t2r1 and t2r0 select timer 2 clock rate. see 9.3 timer 2 for more detail. address: $0010 bit 7654321bit 0 read: tbclk 0 lclk 0 0 0 t2r1 t2r0 write: reset:00000000 figure 7-5. timebase control register 1 (tbcr1) oscillators/cloc k distributions mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 66 freescale semiconductor 7.5.6 timebase c ontrol register 2 read anytime (bits 3 and 0 are write-only bits and always read as logic 0.) write anytime (bit 7 is a read-only bit and writ e has no effect; bit 1 is 1-time write bit.) tbif ? timebase interrupt flag the tbif bit is set every timeout interval of t he timebase counter. this read-only bit is cleared by writing a logic 1 to the rtbif bit. reset clears the tbif bit. the timebase interrupt period between reset and the first tbif depends on the time elapsed during reset, since the timebase divider is not initialized on reset. tbie ? timebase interrupt enable the tbie bit enables the timebase interrupt capabilit y. if tbif = 1 and tbie = 1, the timebase interrupt is generated. 0 = timebase interrupt disabled 1 = timebase interrupt requested when tbif = 1 tbr1 and tbr0 ? timebase interrupt rate select the tbr1 and tbr0 bits select one of four rates for the timebase interrupt period (see table 7-3 ). the tbs rate is also related to the cop timeout reset period. these bits are set to logic 1 on reset. rtbif ? reset tbs interrupt flag the rtbif bit is a write-only bit and is always read as logic 0. writing logic 1 to this bit clears the tbif bit and writing logic 0 to this bit has no effect. bit 2 ? reserved this bit is not used and is always read as logic 0. address: $0011 bit 7654321bit 0 read: tbif tbie tbr1 tbr0 0 0 00 write: rtbif cope copc reset:00110000 = unimplemented figure 7-6. timebase control register 2 (tbcr2) table 7-5. timebase interrupt frequency tbcr2 divide ratio frequency (hz) tbr1 tbr0 osc = 4.0 m osc = 4.1943 m xosc = 32.768 k 00tbclk 128 244 256 256 01tbclk 4096 7.63 8.00 8.00 10tbclk 8192 3.81 4.00 4.00 11tbclk 16,384 1.91 2.00 2.00 timebase mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 67 cope ? cop enable when the cope bit is logic 1, the cop reset function is enabled. this bit is cleared on reset (including cop timeout reset) and write to this bit is allowed only once after reset. copc ? cop clear writing logic 1 to the copc bit clears the 2-bit divider to prevent cop timeout. (the cop timeout period depends on the tbi rate.) this bit is a write-only bit and returns to logic 0 when read. 7.5.7 miscellaneous register ftup ? osc time up flag power-on detection and clearing the fosce bit clears this read-only bit. this bit is set by the overflow of the por counter. reset does not affect this bit. 0 = during por or osc shut down 1 = osc clock available for the system clock stup ? xosc time up flag power-on detection clears this read-only bit. this bit is set after the timebase has counted 8072 clocks. reset does not affect this bit. 0 = xosc not stabilized or no signal on xosc1 and xosc2 pins 1 = xosc clock available for the system clock bits 5 and 4 ? reserved these bits are not used and always read as logic 0. sys1 and sys0 ? system clock select these two bits select the system clock source. on reset, the sys1 a nd sys0 bits are initialized to 1 and 0, respectively. note do not switch the system clock to xosc (sys1 and sys0 = 11) when the xosc clock is not available. the xo sc clock is available when the stup flag is set. do not switch the system clock to osc (sys1 and sys 0 = 00, 01, or 10) when the osc clock is not available. the osc clock is available when the ftup flag is set. address: $003e bit 7654321bit 0 read: ftup stup 0 0 sys1 sys0 fosce optm write: reset:* *001010 = unimplemented * unaffected by reset but initialized by power-on reset figure 7-7. miscellaneous register (misc) oscillators/cloc k distributions mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 68 freescale semiconductor fosce ? fast (main) oscillator enable the fosce bit controls the main oscillator activi ty. this bit should not be cleared by the cpu when the main oscillator is selected as the system clock source. when this bit is cleared: 1. osc is shut down. 2. 7-bit divider at the osc input and por counter are initialized to $0078. 3. ftup flag is cleared. when this bit is set: 1. main oscillator starts again. 2. ftup flag is set by the por counter overflow (8072 clocks). optm ? option map select the optm bit selects one of two register maps at $0000?$000f. this bit is cleared on reset. 0 = main register map selected 1 = option map selected table 7-6. system bus clock frequency selection sys1 sys0 divide ratio cpu bus frequency (hz) osc = 4.0 m osc = 4.1943 m xosc = 32.768 k 00 osc 2 2.0 m 2.0972 m ? 01 osc 4 1.0 m 1.0486 m ? 10osc 64 62.5 k 65.536 k ? 1 1 xosc 2 ? ? 16.384 k mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 69 chapter 8 simple serial peripheral interface (sspi) 8.1 introduction the simple serial peripheral interface (sspi) of t he mc68hc05l16 is a master/s lave synchronous serial communication module. sspi uses a 3-wire protocol: data input, data output, and se rial clock. in this form at, the clock is not being included in the data stream and must be provided as a separate signal. when the sspi is enabled (spe = 1), bits 0?2 of port c become sdi (serial data in), sdo (serial data out), and sck (serial clock) pins. the corresponding ddrc bit does not change the direction of the pin. the mstr bit decides the sspi operation mode. th e sck pin is configured as output in master mode and configured as input in slave mode. the dord bit in the serial peripheral control register (spcr) selects the data transmission order. when dord is set, the least significant bit (lsb) of serial data is shifted out/in first. when the dord is clear, serial data is shifted from/to the most significant bit (msb). master serial clock speed is selected by the spr bit in the spcr. an interrupt may be generated by the completion of a transfer. 8.2 features features of the sspi are: full-duplex, 3-wire synchronous transfers master or slave operation programmable data transmission order, lsb or msb first 1.05-mhz (maximum) transmission bit frequency at 2.1-mhz cpu bus frequency at 5 vdc two programmable transmission bit rates end-of-transmission interrupt flag wakeup from stop mode (slave mode only) 8.3 functional descriptions in master mode, the clock start logic is triggered by the cpu (detection of a cpu write to the 8-bit shift register (spdr)). the sck is based on the internal pr ocessor clock. this clock is also used in the 3-bit counter and 8-bit shift register. see figure 8-2 . when data is written to the 8-bit shift register of the master device, it is then shifted out to the sdo pin for application to the slave device. at the same time, data applied from the slave device via the sdi pin is shifted into the 8-bit shift register. simple serial periph eral interface (sspi) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 70 freescale semiconductor after 8-bit data is shifted in/out, sck stops and spif is set. if spie is enabled, an interrupt request is generated. the slave device in stop mode wakes up by this interrupt. further transfers (writes to spdr) are inhibited while spif is a logic 1. the master-slave basic interc onnection is illustrated in figure 8-1 . figure 8-1. sspi master-slave interconnection 8.4 internal block descriptions this following paragr aphs describe the main blocks in the sspi module. (see figure 8-2 ). figure 8-2. sspi block diagram sck sck sdi sdo sdo sdi spdr hff clock generator spdr hff clock generator master device slave device control logic spsr spcr spdr hff sdo clock generator sck hc05 internal bus interrupt controls and address bus data bus m s t r s p e s t a r t d c o l s p i f sdi dord s p r 000 000000 signal descriptions mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 71 8.4.1 control this block is an interface to the hc05 internal bus and generates a start signal when a write to the spdr is detected in master mode. it also generates an interrupt request to the cpu. 8.4.2 spdr this serial peripheral data register (spdr) is an 8- bit shift register. the dord bit in the spcr determines the bus connection between the internal data bus and spd r. this register can be read and written by the cpu. 8.4.3 spcr bits in the serial peripher al control register (spc r) control sspi functions. 8.4.4 spsr the serial peripheral status register (spsr ) mainly sets flags such as spif and dcol. 8.4.5 clkgen in master mode, this block generates sck when the cpu writes to the data register (spdr) and the clock rate is selected by the spr bit in the control register. in slave mode, the external clock from the sck pin is used instead of the master mode clock, and spr has no affect. this clock generator includes a 3-bit clock c ounter. overflow of this counter sets spif. 8.5 signal descriptions three basic signals ? sdi, sdo, and sck ? are descr ibed in the following subs ections. the relationship among sck, sdi, and sdo is shown in figure 8-3 . 8.5.1 sspi data i/o (sdi and sdo) the two serial data lines ? sdi for input and sdo for output ? are connected to pc0 and pc1, respectively, when sspi is enabled (spe = 1). at the falling edge of sck, a serial data bit is trans mitted out of the sdo pin. at the rising edge of sck, a serial data bit on the sdi pin is sampled internally. when data is transmitted to other devices via the sdo line, the receiving data is shifted into the shift register through the sdi pin. this implies full- duplex transmission with both data-out and data-in synchronized with the same clock signal. thus, the by te transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiv er-full status bits. a single status bit, spif, is used to signify the completion of data transfer. simple serial periph eral interface (sspi) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 72 freescale semiconductor figure 8-3. sspi clock-data timing diagram 8.5.2 serial clock (sck) sck is used for synchronization of both input and output data streams through its sdi and sdo pins. the master and slave devices are capable of exc hanging a data byte during a sequence of eight clock pulses. since the sck is generated by the master, sl ave data transfer is accomp lished by synchronization to sck. the master generates the sck through a circuit driven by the internal processor clock and uses the sck to latch incoming slave device data on the sdi pin and shift out data to the slave via the sdo pin. the spr bit in the spcr of the master selects the transmission clock rate. the slave device receives the sck from the master device, and uses the sck to latch incoming master device data on the sdi pin and shifts out data to the master via the sdo pin. the spr bit in the spcr of the slave has no meaning. note pc2/sck should be at v dd level before sspi is enabled. this can be done with an internal or external pullup re sistor or by setting ddrc2 = 1 and pc2 = 1 prior to enabling the sspi. otherwise , the circuit will not initialize correctly. msb bit6 bit5 bit3 bit2 bit1 lsb bit4 sck sdo dord = 0 msb bit6 bit5 bit3 bit2 bit1 lsb bit4 sdi dord = 0 lsb bit1 bit2 bit4 bit5 bit6 msb bit3 sdo dord = 1 lsb bit1 bit2 bit4 bit5 bit6 bit3 sdi dord = 1 data sample msb registers mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 73 8.6 registers three registers in the sspi provide control, st atus, and data storage f unctions. they are: serial peripheral control register, spcr location $000a serial peripheral status register, spsr location $000b serial peripheral data register, spdr location $000c 8.6.1 serial perip heral control register spie ? sspi interrupt enable if the serial peripheral interrupt enable (spie) bit is set, an interrupt is generated when spif in the spsr is set and i bit (interrupt mask bit) in the condition code regi ster (ccr) is clear. during stop mode, an sspi request is accepted only in slave mode. interrupt in master mode will be pending until stop mode is exited. stop instruction does not change spif and spie. 0 = disable sspi interrupt 1 = enable sspi interrupt spe ? sspi enable when the sspi enable (spe) bit is set, the sspi system is enabled and connected to the port c pins. clearing the spe bit initializes all control logic in the sspi modules and disconnects the sspi from port c pins. this bit is cleared on reset. 0 = disable sspi 1 = enable sspi dord ? data transmission order when this bit is set, the data in the 8-bit shift register (spdr) is shifted in/out from the lsb. when this bit is cleared, the data in the spdr is shifted in/out from the msb. this bit is cleared on reset. 0 = msb first 1 = lsb first mstr ? master mode select the mstr bit determines whether the device is in master mode or slave mode. in master mode (mstr = 1), the sck pin is config ured as an output and the serial clock is generated by the internal clock generator when the cpu writes to the spdr. in slave mode (mstr = 0), the sck pin is config ured as an input and the serial clock is applied externally. this bit is cleared on reset. 0 = slave mode 1 = master mode address: $000a bit 7654321bit 0 read: spie spe dord mstr 0 0 0 spr write: reset:00000000 figure 8-4. serial peripheral control register (spcr) simple serial periph eral interface (sspi) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 74 freescale semiconductor bits 3?1 ? reserved these bits are not used and are fixed to 0. spr ? sspi clock rate select this serial peripheral clock rate bit selects one of two bit rates of sck. this bit is cleared on reset. 0 = internal processo r clock divided by 2 1 = internal processo r clock divided by 16 8.6.2 serial perip heral status register spif ? serial transfer complete flag the serial peripheral data transfer complete flag bit notifies the user that a data transfer between the mc68hc05l16 and an external device has been completed. with the completion of the data transfer, the rising edge of the eighth pulse sets spif, and if spie is set, sspi is generated. however, during stop, the interrupt request is serviced only in slave mode. stop execution never affects the spif flag or spie. when spif is set, the ninth clock from the clock generator or from the sck pin is inhibited. clearing the spif bit is done by a software sequence of accessing the spsr while the spif bit is set followed by accessing spdr (8-bit shift register). this also clears the dcol bit. while spif is set, all writes to the spdr are inhibit ed until spsr is read by the cpu. the spif bit is a read-only bit and is cleared on reset. 0 = data transfer not complete 1 = data transfer complete dcol ? data collision the data collision bit notifies the user that an attempt was made to write or read the serial peripheral data register while a data transfer was taking plac e with an external device. the transfer continues uninterrupted; therefore, a write will be unsuccessful, and a data read will be incorrect. a data collision only sets th e dcol bit and does not generate an sspi interrupt. the dcol bit indicates only the occurrence of data collision. clearing the dcol bit is done by a software sequen ce of accessing the spsr while spif is set followed by accessing the spdr. both the spif and dcol bits will be cleared by this sequence. the dcol bit is cleared on reset. 0 = no data collision 1 = data collision occurred bits 5?0 ? reserved these bits are not used and are fixed to 0. address: $000b bit 7654321bit 0 read:spifdcol000000 write: reset:00000000 = unimplemented figure 8-5. serial peripheral status register (spsr) port function mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 75 8.6.3 serial peripheral data register read a read during transmission causes dcol to be set. write a write during transmission causes dcol to be set. the spdr is used to transmit and receive data on the serial bus. in master mode, a write to this register in itiates transmission/reception of a data byte. the spif status bit is set at the completion of data by te transmission. a write to the spdr is inhibited while this register is shifting (a write attempt sets dcol) or when the spif bit is set without reading spsr. data collision never affects the re ceiving and transmitting data in spdr. a write or read of the spdr after accessing the spsr with spif set will clear the spif and dcol bits. the ability to access the spdr is inhibited when a trans mission is taking place. it is important to read the discussion defining the dcol and spif bits to understand the limits on using the spdr. when sspi is not used (spe = 0), the spdr can be us ed as a general-purpose data storage register. 8.7 port function the sspi shares i/o pins with pc0?pc2. when spe is set, pc0 becomes sdi input, pc1 becomes sdo output and pc2 becomes sck. the direction of sck depends on the mstr bit. setting ddrc bits 0?2 does not change the data direction of the pin to output, but instead changes the source of data when pc0?pc2 is read. if ddrc x = 1, port c bit x data latch is read and if ddrc x = 0, portc x pin level is read by the cpu. when spe is clear, sspi is disconnec ted from the i/o pins and pc0?pc2 are used as general-purpose i/o pins. see 6.4 port c . address: $000c bit 7654321bit 0 read: msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 lsb write: reset: unaffected by reset figure 8-6. serial peripheral data register (spdr) simple serial periph eral interface (sspi) mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 76 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 77 chapter 9 timer system 9.1 introduction the mc68hc05l16 has two timer modules: timer 1 with a 16-bit counter and timer 2 with an 8-bit counter. timer 1 has one input pin (tcap) and no output pin. timer 2 has one input pin (evi) and one output pin (evo). figure 9-1 illustrates the timer system of mc68hc05l16. figure 9-1. timer system block diagram 9.2 timer 1 timer 1 consists of a 16-bit software-programmable co unter driven by a fixed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output compare interrupt. pulse widths can vary from several microseconds to many seconds. see figure 9-2 . tcap input control 1 timer1 timer2 evi input control 2 prescaler timer registers output control evo sel cap clk1 exclk clk2 iedg im2 il2 t2clk o l 2 o e 2 ovf1 cmp1 cmp2 ph2 16-bit counter 8-bit counter timer system mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 78 freescale semiconductor figure 9-2. time r 1 block diagram because the timer has a 16-bit architecture, each spec ific functional segment (capability) is represented by two registers. these registers contain the high by te and low byte of that functional segment. generally, accessing the low byte of a specific timer function al lows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is accessed also. note the i bit in the condition code register (ccr) should be set while manipulating both the high byte and low byte register of a specific timer function to ensure that an interrupt does not occur. input capture register clock internal bus output high byte low byte $16 $17 4 internal processor 16-bit free running counter counter alternate register 8-bit buffer high byte low byte $1a $1b $18 $19 high byte low byte $14 $15 output compare circuit overflow detect circuit edge detect circuit timer status regular $13 icie iedg olvl output level regular reset timer control regular $12 output level (tcmp) interrupt circuit toie ocie edge input d clk c q (not connected to a pin) compare register (tcap) icf ocf tof timer 1 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 79 9.2.1 counter the key element in the programmable timer is a 16-bi t, free-running counter or counter register preceded by a prescaler that divides the internal processor clo ck by four. the prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2. 0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations: $18?$19 (counter register) or $1a?$1b (counter alternate register). a read from only the least significant byte (lsb) of the free-running counter ($19, $1b) receives the count value at the time of the read. if a read of the free-running counter or counter alternate register fi rst addresses the most significant byte (msb) ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains fixed after the first msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter alternate register lsb ($19 or $1b) and, thus, completes a read sequence of the total counter value. in reading either the free-running counte r or counter alternate register, if the msb is read, the lsb must also be read to complete the sequence. the counter alternate register differs from the count er register in one respect: a read of the counter register msb can clear the timer overflow flag (tof). therefore, the counter alternate register can be read at any time without the possibility of missing ti mer overflow interrupts due to clearing of the tof. the free-running counter is configured to $fffc duri ng reset and is always a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator startup delay. because the free-running counter is 16 bits preceded by a fixed divided-by -4 prescaler, the value in the free-running counter repeats every 262,144 internal bu s clock cycles. when the c ounter rolls over from $ffff to $0000, the tof bit is set. an interrupt also can be enabled when counte r roll over occurs by setting its interrupt enable bit (toie). 9.2.2 output compare register the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register is used for severa l purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of th e output compare register can be used as storage locations. the output compare register contents are compared with the contents of the free-running counter continually, and if a match is found, the correspondi ng output compare flag (ocf) bit is set. the output compare register values should be changed after each successful compar ison to establish a new elapsed timeout. an interrupt also can accompany a successful output compare, provided the corresponding interrupt enable bit (ocie) is set. after a processor write cycle to the output compare r egister containing the msb ($16), the output compare function is inhibited until the lsb ($17) also is writte n. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($17) will not inhibit th e compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the outpu t compare register without affecting the other byte. timer system mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 80 freescale semiconductor 9.2.3 input capture register two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the co rresponding input capture edge detector senses a defined transition. the level transition which triggers the counter transfer is defined by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained by an input capture will be one mo re than the value of the free-running counter on the rising edge of the internal bus clock preceding the exte rnal transition. this delay is required for internal synchronization. resolution is one count of the free -running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register ($14) msb, the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time r used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running c ounter transfer since they occur on opposite edges of the internal bus clock. note since the tcap pin is shared with the pc3 i/o pin, changing the state of the pc3 ddr or data register can cause an unwanted tcap interrupt. this can be handled by clearing the icie bi t before changing the configuration of pc3 and clearing any pending interrupts before enabling icie. 9.2.4 timer control register the tcr is a read/write register containing five cont rol bits. three bits enable interrupts associated with the timer status register flags icf, ocf, and tof. icie ? input capture interrupt enable 0 = interrupt disabled 1 = interrupt enabled oc1ie ? output compare 1 interrupt enable 0 = interrupt disabled 1 = interrupt enabled toie ? timer overflow interrupt enable 0 = interrupt disabled 1 = interrupt enabled address: $0012 bit 7654321bit 0 read: icie oc1ie toie 0 0 0 iedg olvl write: reset:000000u0 u = unaffected figure 9-3. timer c ontrol register (tcr) timer 1 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 81 iedg ? input edge the value of the input edge determines which level transition on the tcap pin will trigger free-running counter transfer to the input capture register. reset does not affect the iedg bit. 0 = negative edge 1 = positive edge bits 2?4 ? not used always read logic 0 olvl ? not used always read logic 0 9.2.5 timer status register the tsr is a read-only register c ontaining three status flag bits. icf ? input capture flag 0 = flag cleared when tsr and input capture low register ($15) are accessed 1 = flag set when selected polarity edge is sensed by input capture edge detector oc1f ? output compare 1 flag 0 = flag cleared when tsr and output compare low register ($17) are accessed 1 = flag set when output compare register contents match the free-running counter contents tof ? timer overflow flag 0 = flag cleared when tsr and counter low register ($19) are accessed 1 = flag set when free-running counter transition from $ffff to $0000 occurs bits 0?4 ? not used always read logic 0 accessing the timer status register satisfies the firs t condition required to clear status bits. the remaining step is to access the register corresponding to the status bit. a problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. the timer status register is read or written when tof is set. 2. the lsb of the free-running counter is read but not for the purpose of servicing the flag. the counter alternate register at address $1a and $1b contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. address: $0013 bit 7654321bit 0 read:icfoc1ftof00000 write: reset:uuu00000 = unimplemented u = unaffected figure 9-4. timer stat us register (tsr) timer system mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 82 freescale semiconductor 9.2.6 timer during wait mode the cpu clock halts during wait mode, but timer 1 remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. 9.2.7 timer during stop mode in stop mode, timer 1 stops counting and holds the last count value if stop is exited by an interrupt. if reset is used, the counter is forced to $fffc. during stop, if at least one valid input capture edge occurs at the tcap pin, the input capture detect circuit is armed. this does not set any timer flags or wake up the mcu. when the mcu does wake up, there is an active input capture flag and data from the first valid edge that occurred during stop mode. if reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. 9.3 timer 2 timer 2 is an 8-bit event counter which has one co mpare register, one event input pin (evi), and one event output pin (evo). the event counter is clocked by the external clock (exclk) or prescaled system clock (clk2), selected by the t2clk bit in the tcr2 register. the exclk may be evi direct or evi gated by clk2, which is selected by the im2 bit at the evi block (see 9.3.6 timer input 2 (evi) ). timer 2 may be used as a modulus clock divider wi th evo pin, free-running counter (when compare register is $00), or periodic interrupt timer. the timer counter 2 (tcnt2) is an 8-bit up counter with preset input. the counter is preset to $01 by a cmp2 signal from the comparator or by a cpu write to it that is done while the system clock (ph2) is low. figure 9-5. time r 2 block diagram counter 2 comparator 2 register (oc2) buffer 2 s e l transfer transfer $01 $01 0 1 counter write clk2 exclk t2clk cmp2 timer 2 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 83 figure 9-6. timer 2 timing di agram for f(ph2) > f(timclk) n n 01 counter2 ph2 timclk oc2 (buffer) cmp2 evo compare oc2 = 2, 3, 4 . . . ff, 0 01 01 01 count up count up count up compare oc2 = 1 preset count up count up count up counter2 ph2 timclk oc2 (buffer) cmp2 evo preset preset preset timer system mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 84 freescale semiconductor figure 9-7. timer 2 timing di agram for f(ph2) = f(timclk) n-1 n 02 counter2 ph2 timclk oc2 (buffer) cmp2 evo 3 oc2 = 2, 3, 4 . . . ff, 0 oc2 = 1 legend: count up compare preset that overrides count up legend: count up compare preset that overrides count up n01 1 1 11 22 2 2 01 01 01 counter2 ph2 timclk oc2 (buffer) cmp2 evo 3 01 01 1 1 11 22 2 2 3 3 3 timer 2 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 85 the clk2 from the prescaler or the extclk from the evi block is selected as timer clock by the t2clk bit in the tcr2 register. the clk2 and the exclk ar e synchronized to the falling edge of system clock in the prescaler and the evi blocks. the minimum pulse width of clk2 is the same as the system clock, and the minimum pulse width of exclk (event mode) is one ph2 cycle. when the exclk (event mode) is selected, 50% duty is not guaranteed. the counter is incremented by the falling edge of the timer clock and the period between two falling edges is defined as one timer cycle in the following description. the compare register (oc2) is provided for comparison with the timer counter 2 (tcnt2). the oc2 data is transferred to the buffer register when the counter is preset by a cpu write or by a compare output (cmp2). this buffer register is compared with the timer counter 2 (tcnt2). the comparison between the counter and the oc2 buffer register is done when the system clock is high in each bus cycle. if the counter matches with the oc2 buffer register, the comparator latches this result during the current timer cycle. when the next timer cycle begins, the comparator outputs cmp2 signal (if the compare match is detected during pr evious timer cycle). this cmp2 is used in the counter preset data transfer to the buffer register, setting oc2f in the tsr2 and the evo block. the counter preset overrides the counter increment. the oc2f bit may generate interrupt requests if the oc2ie bit in the tcr2 is set. 9.3.1 timer control register 2 ti2ie ? timer input 2 interrupt enable the ti2ie bit enables timer input 2 (evi) interrupt when ti2f is set. this bit is cleared on reset. 0 = timer input 2 interrupt disabled 1 = timer input 2 interrupt enabled oc2ie ? compare 2 interrupt enable the oc2ie bit enables compare 2 (cmp2) interrupt when compare match is detected (oc2f is set). this bit is cleared on reset. 0 = timer input 2 interrupt disabled 1 = timer input 2 interrupt enabled bit 5 ? reserved this bit is not used and is always read as logic 0. t2clk ? timer 2 clock select the t2clk bit selects the clock source for the timer counter 2. this bit is cleared on reset. 0 = clk2 from prescaler selected 1 = exclk from evi input block selected address: $001c bit 7654321bit 0 read: ti2ie oc2ie 0 t2clk im2 il2 oe2 ol2 write: reset:00000000 figure 9-8. timer cont rol register 2 (tcr2) timer system mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 86 freescale semiconductor im2 ? timer input 2 mode select the im2 bit selects whether evi input is gated or not gated by clk2. this bit is cleared on reset. 0 = evi not gated by clk2 (event mode) 1 = evi gated by clk2 (gate mode) il2 ? timer input 2 active edge (level) select the il2 bit selects the active edge of evi to increment the counter for event mode (im2 = 0) or gate enable level of evi for gate mode (im2 = 1). this bit is cleared on reset. 0 = falling edge selected (event mode) low level enables counting (gate mode) 1 = rising edge selected (event mode) high level enables counting (gate mode) oe2 ? timer output 2 (evo) output enable the oe2 bit enables evo output on the pc5 pin. when th is bit is changed, control of the pin is delayed (synchronized) until the next active edge of evo is se lected by the ol2 bit. this bit is cleared on reset. 0 = evo output disabled 1 = evo output enabled ol2 ? timer output 2 edge select for synchronization the ol2 bit selects which edge of evo clock should be synchronized by the oe2 bit control. the ol2 bit also decides the initial value of the cmp2 divider, when counter 2 is written to by the cpu. this bit is cleared on reset. 0 = the falling edge of evo switches evo output and pc5 if the oe2 bit has been changed. 1 = the rising edge of evo switches evo output and pc5 if the oe2 bit has been changed. table 9-1. evi modes selection im2 il2 action on clock 0 0 falling edge of evi increments counter 0 1 rising edge of evi increments counter 1 0 low level on evi enables counting 1 1 high level on evi enables counting timer 2 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 87 9.3.2 timer status register 2 ti2f ? timer input 2 (evi) interrupt flag in event mode, the event edge sets ti2f. in gated time accumulation mode, the trailing edge of the gate signal at the evi input pin sets ti2f. when th e ti2ie bit and this bit are set, an interrupt is generated. this bit is a read-only bit and writes have no effect. the ti2f is cleared by writing a logic 1 to the rti2f bit and on reset. oc2f ? compare 2 interrupt flag the oc2f bit is set when compare match is detected between counter 2 and oc2 register. when oc2ie bit and this bit are set, an interrupt is generated. this bit is a read-only bit and writes have no effect. the oc2f is cleared by writi ng a logic 1 to roc2f bit and on reset. bits 5 and 4 ? reserved these bits are not used and always read as logic 0. rti2f ? reset timer input 2 flag the rti2f bit is a write-only bit and always reads as l ogic 0. writing logic 1 to this bit clears the ti2f bit and writing a logic 0 to this bit has no effect. roc2f ? reset output compare 2 flag the roc2f bit is a write-only bit and always reads as logic 0. writing logic 1 to this bit clears the oc2f bit and writing a logic 0 to this bit has no effect. bits 1 and 0 ? reserved these bits are not used and always read as logic 0. 9.3.3 output co mpare register 2 the oc2 register data is transferred to the buffer register when the cpu writes to tcnt2, when the cmp2 presets the tcnt2, or when system resets. when the oc2 buffer register matches the tcnt2 regist er, the oc2f bit in the tsr2 register is set and tcnt2 is preset to $01. address: $001d bit 7654321bit 0 read: ti2f oc2f 00 00 00 write: rti2f roc2f reset:00000000 = unimplemented figure 9-9. timer stat us register 2 (tsr2) address: $001e bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 9-10. output co mpare register 2 (oc2) timer system mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 88 freescale semiconductor 9.3.4 timer counter register 2 tcnt2 is incremented by the falling edge of the ti mer clock, which is synchronized and has the same timing as the falling edge of ph2. the tcnt2 register is compared with the oc2 buffer regi ster and initialized to $01 if it matches. it is also initialized to $01 on reset and any cpu write to this register. the cpu read of this counter should be done while ph2 is high. data may be latched by the local or main data bus while ph2 is low. 9.3.5 timebase c ontrol register 1 t2r1/t2r0 ? prescale rate select bits for timer 2 the t2r1 and t2r0 bits select prescale rate of clk2 for timer 2 and timer input 2. these bits are cleared on reset. address: $001f bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000001 figure 9-11. timer count er register 2 (tcnt2) address: $0010 bit 7654321bit 0 read: tbclk 0 lclk 0 0 0 t2r1 t2r0 write: reset:00000000 figure 9-12. timebase cont rol register 1 (tbcr1) table 9-2. timebase prescale rate selection t2r1 t2r0 system clock divided by 00 1 01 4 10 32 11 256 timer 2 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 89 9.3.6 timer input 2 (evi) the event input (evi) is used as an external clock input for timer 2. figure 9-13. evi block diagram since the external clock may be asynchronous to the in ternal clock, this input has a synchronizer which samples external clock by the internal system clock. (the input transition synchronizes to the falling edge of ph2. therefore, to be measured, the minimum pulse width for evi must be larger than one system clock.) the im2 and il2 bits in the tcr2 determine how this synchronized external cl ock is used. the im2 bit decides between event mode and gate mode, and the i l2 bit decides which level or edge is activated. in event mode (im2 = 0), the external clock drives the timer 2 counter directly and the active edge at the evi pin is selected by the il2 bit. when an active edge is detected, the ti2f bit in the tcr2 is set. note since the evi pin is shared with the pc4 i/o pin, ddrc4 should always be cleared whenever evi is used. evi should not be used when ddrc4 is high. in gate mode (im2 = 1), the evi input is gated by clk2 from the prescaler and gate output drives the timer 2 counter. the il2 bit decides active level of the ex ternal input. when the transit ion from active level to inactive level is detected, the ti2f bit is set. changing the im2 bit may cause an illegal count up of tcnt2, thus presetting tcnt2 after initializing im2 is required. table 9-3. evi modes selection im2 il2 action on clock 0 0 falling edge of evi increments counter 0 1 rising edge of evi increments counter 1 0 low level on evi enables counting 1 1 high level on evi enables counting pc4 evi sync active edge/level selector gate/event mode control pc4 ph2 il2 im2 clk2 to ti2f exclk timer system mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 90 freescale semiconductor figure 9-14. evi timing diagram x+1 x+2 counter ph2 exclk il2 = 0 im2 = 0 event mode evi x x+1 x+2 counter exclk il2 = 1 x counter clk2 exclk il2 = 0 im2 = 1 gate mode evi synchronized counter exclk il2 = 1 timer 2 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 91 9.3.7 event output (evo) the evo pin is the clock output pin of timer 2. the compare output from the timer 2 (cmp2) is divided in this block for 50% duty output signal. this 1/2 divider is initialized to the level of the ol2 bit when the timer counter 2 is written to by the cpu (initialized). when t he oe2 bit in the timer control register 2 (tcr2) is set, the evo output is activated, and, when oe2 is cl eared, evo is deactivated. these controls must be done synchronously to the evo output si gnal to avoid an incomplete pulse on the pin. the ol2 bit in the tcr2 decides which edge of evo should be synchronized. when the ddrc5 bit is set or the synchronized output enable is high (clock on), the output buffer at the evo/pc5 pin is enabled. if the ddrc5 bit is set to 1, the pin state during the idli ng condition (clock off) depends on the pc5 output data latch. if the ddrc5 bit is cleared, the pin becomes high impedance during clock off. figure 9-15. evo block diagram 1/2 d c q sel pc5 evo oe2 ol2 cmp2 cntr2 write pc5 (out) pc5 (in) ddrc5 1 0 timer system mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 92 freescale semiconductor figure 9-16. evo timing diagram pc5 = 0/evo oe2 cmp2/2 ol2 = 0 cmp2 evo pc5 = 1/evo oe2 cmp2/2 ol2 = 1 cmp2 evo cntr2 write prescaler mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 93 9.4 prescaler the 8-bit prescaler in the timer system divides sy stem clock (ph2) and provides divided clock to each timer and event input. clk1 for timer 1 is a fixed frequency clock (ph2/ph4). clk2 for timer 2 is selected by t2r1 and t2r0 bits in the tbcr1, and this clock is also used as the event input for gate mode. the clk2 transitions must be synchronous to the falling edge of ph2. figure 9-17. prescaler block diagram table 9-4. timebase prescale rate selection t2r1 t2r0 system clock divided by 00 1 01 4 10 32 11 256 8-bit divider sel 1111 1432256 t2r1 t2r0 clk2 for timer 2 clk1 for timer 1 1 4 rst ph2 timer system mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 94 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 95 chapter 10 lcd driver 10.1 introduction the liquid crystal display (lcd) driver may be conf igured with four backplanes (bp) and 39 frontplanes (fp) maximum. the v dd voltage is the highest level of the output waveform and the lower three levels are applied from vlcd1, vlcd2, and vlcd3 inputs. on reset, lcd enable bit (lcde) in the lcd contro l register (lcdcr) is cleared (lcd drivers at a disabled state) and all bp pins and fp pins output v dd levels. the lcd clock is generated by the timebase module, and the lclk bit in the tbcr1 selects the clock frequency. 10.2 lcd waveform examples figure 10-1 , figure 10-2 , figure 10-3 , and figure 10-4 illustrate the lcd timing examples. figure 10-1. lcd 1/1 duty and 1/1 bias timing diagram 1frame duty = 1/1 (static) bias = 1/1 (vlcd1 = v dd , vlcd2 = vlcd3 = v dd ?vlcd) bp0 fpx (xxx1) fpy (xxx1) bp0?fpx (off) bp0?fpy (on) v dd , vlcd1 vlcd2, 3 v dd , vlcd1 vlcd2, 3 v dd , vlcd1 vlcd2, 3 +vlcd 0 ?vlcd +vlcd 0 ?vlcd lcd driver mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 96 freescale semiconductor figure 10-2. lcd 1/2 duty and 1/2 bias timing diagram duty = 1/2 bias = 1/2 (vlcd1 = vlcd2 = v dd ?vlcd/2, vlcd3 = v dd ?vlcd) fpy (xx00) fpx (xx01) bp0?fpy (off) v dd bp1?fpx (off) 1 frame bp0 vlcd1, 2 vlcd3 bp1 v dd vlcd1, 2 vlcd3 v dd vlcd1, 2 vlcd3 v dd vlcd1, 2 vlcd3 vlcd vlcd/2 0 ?vlcd/2 ?vlcd vlcd vlcd/2 0 ?vlcd/2 ?vlcd bp0?fpx (on) vlcd vlcd/2 0 ?vlcd/2 ?vlcd lcd waveform examples mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 97 figure 10-3. lcd 1/3 duty and 1/3 bias timing diagram 1frame duty = 1/3 bias = 1/3 (vlcd1 = v dd ?vlcd/3, vlcd2 = v dd ?2vlcd/3, vlcd3 = v dd ?vlcd) bp0 fpx (x010) v dd vlcd1 vlcd3 v dd vlcd2 vlcd3 v dd vlcd1 vlcd2 vlcd3 v dd vlcd1 bp1?fpx (on) +2vlcd/3 +vlcd/3 ?vlcd/3 ?2vlcd/3 ?vlcd +vlcd +2vlcd/3 +vlcd/3 0 ?vlcd/3 vlcd2 vlcd1 vlcd2 vlcd3 +vlcd 0 ?2vlcd/3 ?vlcd bp1 bp0?fpx (off) bp2 lcd driver mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 98 freescale semiconductor figure 10-4. lcd 1/4 duty and 1/3 bias timing diagram 1frame duty = 1/4 bias = 1/3 (vlcd1 = v dd ?vlcd/3, vlcd2 = v dd ?2vlcd/3, vlcd3 = v dd ?vlcd) bp0 fpx (1001) v dd vlcd1 vlcd3 v dd vlcd2 vlcd3 v dd vlcd1 vlcd2 vlcd3 v dd vlcd1 vlcd1 vlcd2 +vlcd +2vlcd/3 +vlcd/3 0 ?vlcd/3 ?2vlcd/3 ?vlcd +vlcd/3 vlcd2 vlcd1 vlcd2 vlcd3 v dd vlcd3 0 ?vlcd/3 bp1 bp1?fpx (off) bp2 +vlcd +2vlcd/3 ?2vlcd/3 ?vlcd bp3 bp0?fpx (on) backplane driver and port selection mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 99 10.3 backplane driver and port selection the number of backplane (port d) pins depends on the lcd duty. it is automatically selected by duty1 and duty0 bits in the lcd control register (lcdcr). on reset, these bits are cleared and 1/4 duty is selected. (see table 10-1 .) 10.4 frontplane driver and port selection the number of frontplane (fp) pins depends on the numb er of port d and port e bits. if port bits are selected as a parallel output port, the number of the fp pins is decreased to 27 as a minimum. the selections between frontplane and port (nibble wide) are done by the peh, pel, and pdh bits in the lcdcr (see table 10-2 ). these bits also can be controlled on a bit-wide basis by using the pdmux and pemux registers. pdh, peh, and pel have priority over the mux registers. on reset, port d and port e bits are disconnected and fp27?fp38 pins output v dd levels. table 10-1. backplane and port selection duty lcd control pin selection duty1 duty0 bp3/pd3 bp2/pd2 bp1/pd1 bp0 1 / 10 1pd3pd2pd1bp0 1 / 2 1 0 pd3 pd2 bp1 bp0 1 / 3 1 1 pd3 bp2 bp1 bp0 1 / 4 0 0 bp3 bp2 bp1 bp0 table 10-2. frontplane and port selection fp / port control port selection peh pel pdh pdmx pemx fp27:fp30/ pe7:pe4 fp31:fp34/ pe3:pe0 fp35:fp38/ pd7:pd4 00 fp35:fp38 01 varied 1 x pd7:pd4 00fp31:fp34 01varied 1 x pe3:pe0 00fp27:fp30 011varied 1 x x pe7:pe4 lcd driver mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 100 freescale semiconductor 10.5 lcd control register lcde ? lcd output enable the lcde bit enables all bp and fp outputs. (this bit does not affect peh, pel, or pdh bits.) this bit is cleared on reset. 0 = all dedicated fp pins output highest (v dd ) level; bp and fp pins are shared with an output port data. 1 = all bp and fp pins output lcd waveforms. duty1 and duty0 ? lcd duty select the duty1 and duty0 bits select the duty of the lcd driver. the number of bp pins is related to this duty selection. the unused bp pin is used as a port d pin. default duty is 1/4 duty. these bits are cleared on reset. see table 10-1 . bit 4 ? reserved this bit is not used and always reads as logic 0. peh ? select port e (h) the peh bit enables the upper four bits of port e inst ead of lcd drivers. this bit is cleared on reset. see 10.4 frontplane driver and port selection . 0 = fp27?fp30 selected 1 = pe7?pe4 selected pel ? select port e (l) the pel bit enables the lower four bits of port e in stead of lcd drivers. this bit is cleared on reset. see 10.4 frontplane driver and port selection . 0 = fp31?fp34 selected 1 = pe3?pe0 selected pdh ? select port d (h) the pdh bit enables the upper four bits of port d instead of lcd drivers. this bit is cleared on reset. see 10.4 frontplane driver and port selection . 0 = fp35?fp38 selected 1 = pd7?pd4 selected bit 0 ? reserved this bit is not used and is always read as logic 0. address: $0020 bit 7654321bit 0 read: lcde duty1 duty0 0 peh pel pdh 0 write: reset:00000000 figure 10-5. lcd control register (lcdcr) lcd data register mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 101 10.6 lcd data register lcdrx ? lcd data registers data in the lcdr x (lcdr1?lcdr20) controls the waveform of the two frontplane drivers. bits 0?3 and bits 4?7 of this register decide the waveforms at the bp0?bp3 timings. if the lcd duty is not 1/4, the register bit for the unused backplane has no m eaning. the upper four bits of lcdr20 are not implemented and unknown data may be read. (see table 10-3 .) 0 = output deselect waveform at the corresponding backplane timing 1 = output select waveform at the corresponding backplane timing address: $0021?$0034 fp (2x?1) fp (2x?2) bit 7654321bit 0 read: bp3 bp2 bp1 bp0 bp3 bp2 bp1 bp0 write: reset: unaffected by reset figure 10-6. ldc data registers table 10-3. frontplane data register bit usage duty frontplane data register bit usage bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 / 1???bp0???bp0 1 / 2 ? ? bp1 bp0 ? ? bp1 bp0 1 / 3 ? bp2 bp1 bp0 ? bp2 bp1 bp0 1 / 4 bp3 bp2 bp1 bp0 bp3 bp2 bp1 bp0 lcd driver mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 102 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 103 chapter 11 instruction set 11.1 introduction the microcontroller unit (mcu) instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos (complementary metal-oxide semiconductor) family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 11.2 addressing modes the central processor unit (cpu) uses eight addressi ng modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 11.2.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in th e cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 11.2.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instruct ions require no operand addres s and are two bytes long. the opcode is the first byte, and the i mmediate data value is the second byte. 11.2.3 direct direct instructions can access any of the first 256 me mory locations with two byte s. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. instruction set mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 104 freescale semiconductor 11.2.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 11.2.5 indexed, no offset indexed instructions with no offset are 1-byte inst ructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as t he high byte, so these instructions can address locations $0000?$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used random-access memory (ram) or input/output (i/o) location. 11.2.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instru ctions that can access data with variable addresses within the first 511 memo ry locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the e ffective address of the operand. these instructions can access locations $0000?$01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory lo cations and could extend as far as location 510 ($01fe). the k value is typically in the index regist er, and the address of the beginning of the table is in the byte following the opcode. 11.2.7 indexed, 16-bit offset indexed, 16-bit offset instructions are 3-byte instruct ions that can access data with variable addresses at any location in memory. the cpu adds the unsigned by te in the index register to the two unsigned bytes following the opcode. the sum is the effective addres s of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for se lecting the kth element in an n-element table anywhere in memory. as with direct and extended address ing, the freescale assembler determines the shortest form of indexed addressing. 11.2.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two?s complement byte that gives a branching range of ?128 to +127 bytes from the address of the next location after the branch instruction. when using the freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. instruction types mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 105 11.3 instruction types the mcu instructions fall in to these five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions 11.3.1 register/memory instructions these instructions operate on central processor unit (cpu) registers and memory locations. most of them use two operands. one operand is in either the accumula tor or the index register. the cpu finds the other operand in memory. table 11-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub instruction set mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 106 freescale semiconductor 11.3.2 read-modify-w rite instructions these instructions read a memory location or a regist er, modify its contents, and write the modified value back to the memory location or to the register. note do not use read-modify-write operations on write-only registers. table 11-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-wri te instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one?s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two?s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence because it does not write a replacement value. instruction types mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 107 11.3.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch bas ed on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be test ed is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the test ed bit to the carry/borrow bit of the condition code register. table 11-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr instruction set mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 108 freescale semiconductor 11.3.4 bit manipul ation instructions the cpu can set or clear any writable bit in the fi rst 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. 11.3.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 11-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset table 11-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait instruction set summary mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 109 11.4 instruction set summary table 11-6. instruction se t summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a (a) (m) ? ? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ? ? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ? ? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bclr n opr clear bit n mn 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 ????? rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 ????? rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 ????? rel 22 rr 3 bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ????? rel 2e rr 3 c b0 b7 0 b0 b7 c instruction set mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 110 freescale semiconductor bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ? ? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 ????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 ????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 ????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 ????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 ????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 ????? rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ????? rel ad rr 6 clc clear carry bit c 0 ???? 0 inh 98 2 cli clear interrupt mask i 0 ? 0 ??? inh 9a 2 table 11-6. instruction se t summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc instruction set summary mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 111 clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 ?? 0 1 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ? ? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) ?? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ? ? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ? ? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc effective address ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 table 11-6. instruction se t summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc instruction set mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 112 freescale semiconductor lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ? ? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ? ? ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ? ? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ? ? 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 ??? 0 inh 42 1 1 neg opr nega negx neg opr ,x neg ,x negate byte (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ? ? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ? ? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ? ? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff ? ???? inh 9c 2 table 11-6. instruction se t summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 b0 b7 c instruction set summary mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 113 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ? (m) ? (c) ? ? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 ???? 1 inh 99 2 sei set interrupt mask i 1 ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ? ? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin ? 0 ? ? ? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ? ? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ? (m) ? ? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ? 1 ??? inh 83 1 0 tax transfer accumulator to index register x (a) ????? inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ? ? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 table 11-6. instruction se t summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc instruction set mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 114 freescale semiconductor 11.5 opcode map see table 11-7 . txa transfer index register to accumulator a (x) ????? inh 9f 2 wait stop cpu clock and enable interrupts ? 0 ? ? ? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch p rogram counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit o ffset addressing rr relative pr ogram counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix1 indexed, 8-bit offset addressing mode loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit ? not affected table 11-6. instruction se t summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 115 opcode map table 11-7. opcode map bit manipulation branch read-modif y-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3 ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3 ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3 ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3 ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3 ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3 ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3 ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 ta x 1inh 4 sta 2dir 5 sta 3 ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3 ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3 ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3 ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3 ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3 ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3 ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3 ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3 ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb instruction set mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 116 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 117 chapter 12 electrical specifications 12.1 introduction this section contains parametric and timing information. 12.2 maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in this table. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note this device is not guaranteed to operate properly at the maximum ratings. refer to 12.6 5.0-volt dc electrical characteristics and 12.7 3.3-volt dc electrical characteristics for guaranteed operating conditions. rating symbol value unit supply voltage v dd v lcd1 v lcd2 v lcd3 ?0.3 to +7.0 v ss ?0.3 to v dd +0.3 v ss ?0.3 to v dd +0.3 v ss ?0.3 to v dd +0.3 v input voltage v in v ss ?0.3 to v dd + 0.3 v self-check mode (irq1 pin only) v in v ss ?0.3 to 2 x v dd + 0.3 v output voltage v out v ss ?0.3 to v dd + 0.3 v current drain per pin excluding v dd and v ss i12.5ma operating junction temperature t j +150 c storage temperature range t stg ?55 to +150 c electrical specifications mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 118 freescale semiconductor 12.3 operating temperature range 12.4 thermal characteristics 12.5 recommended operating conditions characteristic symbol value unit operating temperature range mc68hc05l16 (standard) mc68hc05l16c (extended) t a t l to t h 0 to +70 ?40 to +85 c characteristic symbol value unit thermal resistance 80-pin plastic quad flat pack ja 120 c/w rating (1) 1. +2.2 v dd +5.5 vdc, v ss = 0 vdc, t l t a t h , unless otherwise noted symbol min typ max unit supply voltage (f op = 2.1 mhz) v dd 4.5 5.0 5.5 v (f op = 1.0 mhz) v dd 2.2 ? 5.5 v v lcd1 v dd ? 1/3 v lcd v v lcd2 v dd ? 2/3 v lcd v v lcd3 v dd ? 3/3 v lcd v fast clock oscillation frequency f osc ? 3.52 4.2 mhz external capacitance (f osc = 3.52 mhz) c1 c2 ? ? 33 33 ? ? pf slow clock oscillation frequency f xosc ? 32.768 ? mhz external capacitance (f xosc = 32.768 khz) cx1 cx2 ? ? 18 22 ? ? pf 5.0-volt dc electrical characteristics mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 119 12.6 5.0-volt dc el ectrical characteristics characteristic (1) 1. +4.5 v dd +5.5 vdc, v ss = 0 vdc, t l t a t h , unless otherwise noted. all values shown reflect average measure- ments. typical values at midpoint of voltage range, 25 c only. symbol min typ max unit output voltage i load = 10.0 a i load = ?10.0 a v ol v oh ? v dd ?0.1 ? ? 0.1 ? v output high voltage (v dd = 5.0 v) (i load = ?0.4 ma) pa0?pa7, pc0?pc5, pd1?pd7, pe0?pe7 v oh v dd ?0.8 ??v output low voltage (v dd = 5.0 v) (i load = 0.8 ma) pa0?pa7, pc0?pc7, pd1?pd7, pe0?pe7 v ol ??0.4v input high voltage pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 v ih 0.7 x v dd ? v dd v input low voltage pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 v il v ss ? 0.3 x v dd v supply current (2), (3), (4), (5) run (f op = 2.1 mhz) wait (f op = 2.1 mhz) stop no clock xosc = 32.768 khz, v dd = 5.0 v, t a = +25 o c 2. run (operating) i dd , wait i dd ; measured using external square wave clock source (f osc = 4.2 mhz); all inputs 0.2 v from rail (v ss or v dd ); no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 3. wait, stop i dd ; all ports configured as inputs; v il = 0.2 v; v ih = v dd ?0.2 v 4. stop i dd measured with osc1 = v ss . 5. wait i dd is affected linearly by the osc2 capacitance. i dd ? ? ? ? 6.0 3.0 3.0 17.0 12.0 6.0 10.0 ? ma ma a a input current (6) (with pullups disabled) pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 6. input current is measured with output transistor turned off and v in = 0 v. i in ?? 1.0 a input current (6) (with pullups enabled, v dd = 5.0 v) pa0?pa7 pb0?pb7 pc0?pc5 pc6?pc7 i in 50 50 200 30 180 180 700 125 400 400 1400 300 a a a a lcd pin output impedance fp0?fp26 bp0?bp3 zo, fp zo, bp ? ? 10 5 20 18 k ? k ? electrical specifications mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 120 freescale semiconductor 12.7 3.3-volt dc el ectrical characteristics characteristic (1) 1. +3.0 v dd < +4.5 vdc, v ss = 0 vdc, t l t a t h , unless otherwise noted. all values shown reflect average measurements. typical values at midpoint of voltage range, 25 c only. symbol min typ max unit output voltage i load = 10.0 a i load = ?10.0 a v ol v oh ? v dd ?0.1 ? ? 0.1 ? v output high voltage (v dd = 3.5 v) (i load = ?0.4 ma) pa0?pa7, pc0?pc5, pd1?pd7, pe0?pe7 v oh v dd ?0.8 ??v output low voltage (v dd = 3.5 v) (i load = 0.8 ma) pa0?pa7, pc0?pc7, pd1?pd7, pe0?pe7 v ol ??0.4v input high voltage pa0?pa7, pb0?pb7, pc0?pc7, reset ,osc1, xosc1 v ih 0.7 x v dd ? v dd v input low voltage pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 v il v ss ? 0.3 x v dd v supply current (2), (3), (4), (5) run (f op = 1.0 mhz) wait (f op = 1.0 mhz) stop no clock xosc = 32.768 khz, v dd = 3.0 v, t a = +25 o c 2. run (operating) i dd , wait i dd ; measured using external square wave clock source (f osc = 2.0 mhz); all inputs 0.2 v from rail (v ss or v dd ); no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 3. wait, stop i dd ; all ports configured as inputs; v il = 0.2 v; v ih = v dd ?0.2 v 4. stop i dd measured with osc1 = v ss . 5. wait i dd is affected linearly by the osc2 capacitance. i dd ? ? ? ? 1.8 0.8 2.0 8.0 4.0 2.0 10.0 ? ma ma a a input current (6) (with pullups disabled) pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 6. input current is measured with out put transistor turned off and v in = 0 v. i in ?? 1.0 a input current (6) (with pullups enabled, v dd = 3.3 v) pa 0 ? pa 7 pb0?pb7 pc0?pc5 pc6?pc7 i in 20 20 50 30 75 75 300 100 300 300 1000 250 a a a a lcd pin output impedance fp0?fp26 bp0?bp3 zo, fp zo, bp ? ? 10 5 20 18 k ? k ? 2.7-volt dc electrical characteristics mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 121 12.8 2.7-volt dc el ectrical characteristics characteristic (1) 1. +2.2 v dd < +3.0 vdc, v ss = 0 vdc, t l t a t h , unless otherwise noted. all values shown reflect average measurements. typical values at midpoint of voltage range, 25 c only. symbol min typ max unit output voltage i load = 10.0 a i load = ?10.0 a v ol v oh ? v dd ?0.1 ? ? 0.1 ? v output high voltage (v dd = 2.2 v) (i load = ?0.4 ma) pa0?pa7, pc0?pc5, pd1?pd7, pe0?pe7 v oh v dd ?0.6 ??v output low voltage (v dd = 2.2 v) (i load = 0.4 ma) pa0?pa7, pc0?pc7, pd1?pd7, pe0?pe7 v ol ??0.3v input high voltage pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 v ih 0.7 x v dd ? v dd v input low voltage pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 v il v ss ? 0.3 x v dd v supply current (2), (3), (4), (5) run (f op = 1.0 mhz) wait (f op = 1.0 mhz) stop no clock xosc = 32.768 khz, v dd = 2.2 v, t a = +25 o c 2. run (operating) i dd , wait i dd ; measured using external square wave clock source (f osc = 2.0 mhz); all inputs 0.2 v from rail (v ss or v dd ); no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 3. wait, stop i dd ; all ports configured as inputs; v il = 0.2 v; v ih = v dd ?0.2 v 4. stop i dd measured with osc1 = v ss . 5. wait i dd is affected linearly by the osc2 capacitance. i dd ? ? ? ? 0.7 0.4 1.5 5.0 2.2 1.4 10.0 ? ma ma a a input current (6) (with pullups disabled) pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 6. input current is measured with output transistor turned off and v in = 0 v. i in ?? 1.0 a input current (6) (with pullups enabled, v dd = 2.7 v) pa 0 ? pa 7 pb0?pb7 pc0?pc5 pc6?pc7 i in 5 5 30 20 50 50 200 85 150 150 600 200 a a a a lcd pin output impedance fp0?fp26 bp0?bp3 zo, fp zo, bp ? ? 10 5 20 18 k ? k ? electrical specifications mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 122 freescale semiconductor 12.9 control timing characteristic (1) 1. +2.2 v dd +5.5 vdc, v ss = 0 vdc, t l t a t h , unless otherwise noted. symbol min max unit frequency of oscillation (osc) crystal external clock f osc ? dc 4.2 4.2 mhz internal operating frequency (2) , crystal or external clock (f osc /2) v dd = 4.5 v to 5.5 v v dd = 2.2 v to 5.5 v 2. the system clock divider conf iguration (sys1?sys0 bits ) should be selected such that the inte rnal operating frequency (f op ) does not exceed value specified in f op for a given f osc . f op ? ? 2.1 1.0 mhz cycle time (fast osc selected) v dd = 4.5 v to 5.5 v v dd = 2.2 v to 5.5 v t cyc 480 1.0 ? ? ns s reset pulse width when bus clock active t rl 1.5 ? t cyc timer resolution input capture (tcap) pulse width t resl t th , t tl 4.0 284 ? ? t cyc ns interrupt pulse width low (edge-triggered) t ilih 284 ? ns interrupt pulse period (3) 3. the minimum period, t ilil , should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . t ilil see note ? t cyc osc1 pulse width (external clock input) t oh , t ol 110 ? ns control timing mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 123 figure 12-1. stop recovery timing diagram fffe fffe fffe fffe ffff 4 t rl t ilih osc1 1 reset irq 2 irq 3 internal clock internal address bus t ilch 8092 t cyc notes: 1. represents the internal gating of the osc1 pin 2. irq pin edge-sensitive mask option 3. irq pin level and edge-sensitive mask option 4. reset vector address shown for timing example reset or interrupt vector fetch electrical specifications mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 124 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 125 chapter 13 mechanical specifications 13.1 introduction this section describes the dimens ions of the quad flat pack (qfp). mechanical specifications mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 126 freescale semiconductor 13.2 quad flat pack (qfp) ? case 841b-01 ! " # $! ! $! ! % ! " ! " # ! " " ! & " " $" '( " ! ! " $" " ! " '( % # ! % " " ! $ ! # p -a,b,d- b b detail a f d n section b-b j -h- detail c k q r t w x u ' ( -h- 60 61 80 120 21 40 41 detail c -c- m c h m g -b- -a- -d- b a l s v l e detail a ! ' ( )" ' ( )" )" '( ' ( )" *' ( )" *'( )" " " " " " " # # *' ( ! )" mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 127 chapter 14 ordering information 14.1 introduction this section contains instructions for ordering custom-masked rom mcus. 14.2 mcu ordering forms to initiate an order for a rom-based mcu, first obtain the current ordering form for the mcu from a freescale representative. submit the following items when ordering mcus: a current mcu ordering form that is completely filled out (contact your freescale sales office for assistance.) a copy of the customer specification if the cu stomer specification devia tes from the freescale specification for the mcu customer?s application program on one of the media listed in 14.3 application program media 14.3 application program media please deliver the application program to freescale in one of the following media: macintosh ?(1) 3 1/2-inch diskette (double-sided 800 k or double-sided high-density 1.4 m) ms-dos ?(2) or pc-dos tm (3) 3 1/2-inch diskette (double-sided 720 k or double-sided high-density 1.44 m) ms-dos ? or pc-dos tm 5 1/4-inch diskette (double-sided double-density 360 k or double-sided high-density 1.2 m) use positive logic for data and addresses. when submitting the application prog ram on a diskette, clearly label the diskette with the following information: customer name customer part number project or product name file name of object code date name of operating system that formatted diskette formatted capacity of diskette 1. macintosh is a registered tr ademark of apple computer, inc. 2. ms-dos is a registered trademark of microsoft corporation. 3. pc-dos is a trademark of internat ional business machines corporation. ordering information mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 128 freescale semiconductor on diskettes, the application program must be in fr eescale?s s-record format (s1 and s9 records), a character-based object file format generated by m6805 cross assemblers and linkers. note begin the application program at the first user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory map. write $00 in all non-user rom locations or leave all non-user rom locations blank. refer to the current mcu ordering form for additional requirements. freescale may request pattern re-submission if non-user areas contain any non-zero code. if the memory map has two user rom areas with t he same addresses, then write the two areas in separate files on the diskette. label the diskette with both filenames. in addition to the object code, a file containing the source code can be incl uded. freescale keeps this code confidential and uses it only to expedite rom pattern generation in case of any difficulty with the object code. label the diskette with the filename of the source code. 14.4 rom program verification the primary use for the on-chip rom is to hold the customer?s application program. the customer develops and debugs the application program and then submits the mcu order along with the application program. freescale inputs the customer?s application program code into a computer program that generates a listing verify file. the listing veri fy file represents the memory map of the mcu. the listing verify file contains the user rom code and may also contai n non-user rom code, such as self-check code. freescale sends the customer a computer printout of t he listing verify file along wi th a listing verify form. to aid the customer in checking the listing verify file , freescale will program the listing verify file into customer-supplied blank preformatted macintosh or dos disks. all original pattern media are filed for contractual purposes and are not returned. check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to freescale. the si gned listing verify form constitutes the contractual agreement for the creation of the custom mask. 14.5 rom verification units (rvus) after receiving the signed listing verify form, fr eescale manufactures a custom photographic mask. the mask contains the customer?s appl ication program and is used to proc ess silicon wafers. the application program cannot be changed after the manufacture of the mask begins. freescale then produces 10 mcus, called rvus, and sends the rvus to the cu stomer. rvus are usually packaged in unmarked ceramic and tested to 5 vdc at room temperature. rvus are not tested to environmental extremes because their sole purpose is to demonstrate that the customer?s user rom pattern was properly implemented. the 10 rvus are free of charge with the minimum order quantity. these units are not to be used for qualification or produc tion. rvus are not guaranteed by freescale quality assurance. mc order numbers mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 129 14.6 mc order numbers table 14-1 shows the mc order numbers fo r the available package types. table 14-1. mc order numbers package type operating temperature range mc order number 80-pin plastic quad flat pack (qfp) 0 c to +70 c mc68hc05l16fu ?40 c to +85 c mc68hc05l16cfu ordering information mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 130 freescale semiconductor mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 131 appendix a mc68hc705l16 a.1 introduction the mc68hc705l16 is similar to the mc68hc05l16 wi th the exception of the eprom feature. the program rom on the mc68hc05l16 has been replaced by 16-k electrically programmable read-only memory to allow modification of the program co de for emulation. the entire data sheet of the mc68hc05l16 applies to the eprom part with the additi ons and exceptions explained in this appendix. the additional features available on the mc68hc705l16 are: 16,384 bytes of eprom on-chip bootstrap firmware for programming use self-check mode replaced by bootstrap capability a.2 differences between mc 68hc05l16 and mc68hc705l16 a.3 mcu structure figure a-1 shows the structure of the mc68hc705l16 mcu. a.4 mask options there are no mask options available for the mc68 hc705l16. for this reason, the address option map shown in chapter 2 memory map has no meaning. table a-1. differences between mc68hc05l16 and mc68hc705l16 item mc68hc05l16 mc68hc705l16 rom memory type mask rom eprom internal test mode self-check mode bootstrap mode lcd 1/2 duty 1/2 bias waveform see figure 10-2 see figure a-6 eprom programming not applicable through v pp pin and pcr mask option customer specified no mask option osc, xosc, and reset pin resistor option available by mask option not available mc68hc705l16 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 132 freescale semiconductor figure a-1. block diagram note a line over a signal name indicates an active low signal. for example, reset is active low. pa0 pc5/evo pc6*/irq2 pc7*/irq1 pc0/sdi timebase internal cop cpu m68hc05 cpu alu cpu registers control sram bootstrap rom system system processor clock 496 bytes accumulator index register stack pointer program counter condition code reg 2 pa1 pa2 pa3 pa4 port a data a pa5 pa6 pa7 osc sel lcd drivers eprom reset v dd osc1 osc2 v ss port b data b key wakeup pb0/kwi0 pb1/kwi1 pb2/kwi2 pb3/kwi3 pb6/kwi6 pb7/kwi7 pb5/kwi5 pb4/kwi4 pc1/sdo pc2/sck pc3/tcap pc4/evi port c data c spi timer2 fp0?pf26 port e fp36/pd6 bp0 bp2/pd2 bp1/pd1 fp35/pd7 fp37/pd5 fp38/pd4 bp3/pd3 fp28/pe6 fp34/pe0 fp32/pe2 fp33/pe1 fp27/pe7 fp29/pe5 fp30/pe4 fp31/pe3 port d vlcd3 vlcd2 vlcd1 div v pp ** 16,384 bytes xosc xosc1 xosc2 512 bytes * open drain only when output ** the v pp pin should be connected to v dd in single-chip + 16 bytes dir reg dir reg dir reg functional pin description mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 133 a.5 functional pin description the mc68hc705l16 is available in the 80-pin quad fl at pack (qfp). the pin assignment is shown in figure a-2 . figure a-2. pin assignments for single-chip mode a.6 programming voltage (v pp ) in single-chip (user) mode, the v pp pin should be tied to v dd level. 1 20 40 41 60 61 80 21 v dd fp28/pe6 fp29/pe5 fp30/pe4 fp31/pe3 fp32/pe2 fp33/pe1 fp34/pe0 fp35/pd7 fp36/pd6 fp37/pd5 fp38/pd4 vlcd3 vlcd2 vlcd1 v ss v pp ** xosc1 xosc2 reset v ss fp7 fp6 fp5 fp4 fp3 fp2 fp1 fp0 bp0 bp1/pd1 bp2/pd2 bp3/pd3 v dd pc7*/irq1 pc6*/irq2 pc5/evo pc4/evi pc3/tcap pc2/sck fp27/pe7 fp26 fp25 fp24 fp23 fp22 fp21 fp20 fp19 fp18 fp17 fp16 fp15 fp14 fp13 fp12 fp11 fp10 fp9 fp8 osc1 osc2 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0/kwi0 pb1/kwi1 pb2/kwi2 pb3/kwi3 pb4/kwi4 pb5/kwi5 pb6/kwi6 pb7/kwi7 pc0/sdi pc1/sdo * open drain only when output **the v pp pin should be connect to v dd in single-chip mode. mc68hc705l16 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 134 freescale semiconductor table a-2. pin configuration pin number scm, bootstrap i/o pin number scm, bootstrap i/o 23 24 25 26 27 28 29 30 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 i/o i/o i/o i/o i/o i/o i/o i/o 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 fp0 fp1 fp2 fp3 fp4 fp5 fp6 fp7 fp8 fp9 fp10 fp11 fp12 fp13 fp14 fp15 fp16 fp17 fp18 fp19 fp20 fp21 fp22 fp23 fp24 fp25 fp26 o o o o o o o o o o o o o o o o o o o o o o o o o o o 31 32 33 34 35 36 37 38 pb0/kwi0 pb1/kwi1 pb2/kwi2 pb3/kwi3 pb4/kwi4 pb5/kwi5 pb6/kwi6 pb7/kwi7 i i i i i i i i 39 40 41 42 43 44 45 46 pc0/sdi pc1/sdo pc2/sck pc3/tcap pc4/evi pc5/evo pc6*/irq2 pc7*/irq1 i/o i/o i/o i/o i/o i/o i i 17 v pp ** i 47 1 60 16 21 22 18 19 v dd v dd v ss v ss osc1 osc2 xosc1 xosc2 i i o o i o i o 80 2 3 4 5 6 7 8 fp27/pe7 fp28/pe6 fp29/pe5 fp30/pe4 fp31/pe3 fp32/pe2 fp33/pe1 fp34/pe0 o o o o o o o o 15 14 13 48 49 50 51 vlcd1 vlcd2 vlcd3 bp3/pd3 bp2/pd2 bp1/pd1 bp0 i i i o o o o 9 10 11 12 fp35/pd7 fp36/pd6 fp37/pd5 fp38/pd4 o o o o *open drain only when output **the v pp pin should be connect to v dd in single-chip mode. modes of operation mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 135 a.7 modes of operation the mc68hc705l16 has the following operating modes : single-chip mode (scm) and bootstrap mode. single-chip mode, also called user mode, allows ma ximum use of pins for on -chip peripheral functions. the bootstrap mode is provided for eprom progr amming, dumping eprom contents, and loading programs into the internal ram and executing t hem. this is a versatile mode because there are essentially no limitations on the special-purpose program that is boot-loaded into the internal ram. a.7.1 mode entry mode entry is done at the rising edge of the reset pin. once the device enters one of the modes, the mode cannot be changed by software. only an external reset can change the mode. at the rising edge of the reset pin, the device latches the states of irq1 and irq2 and places itself in the specified mode. while the reset pin is low, all pins are co nfigured as single-chip mode. table a-3 shows the states of irq1 and irq2 for each mode entry. high voltage v tst = 2 x v dd is required to select modes other than single-chip mode. figure a-3. mode entry diagram a.7.2 single-chip mode (scm) in this mode, all address and data bus ac tivity occurs within the mcu. t hus, no external pins are required for these functions. the single-chip mode allows the maximum number of i/o pins for on-chip peripheral functions, for example, ports a through e, and lcd drivers. table a-3. mode select summary modes reset pc6/irq1 pc7/irq2 single-chip (user) mode v ss or v dd v ss or v dd bootstrap mode v tst v dd v tst v dd v ss v dd v ss irq2 irq1 reset single-chip mode v tst = 2 x v dd v dd v ss mc68hc705l16 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 136 freescale semiconductor a.7.3 bootstrap mode in this mode, the reset vector is fetched from a 496-byte internal bootstrap rom at $fe00?$ffef. the bootstrap rom contains a small program which loads a program into the internal ram and then passes control to that program at location $0040 or executes the eprom programming sequence and dumps eprom contents. since these modes are not normal user modes, all of t he privileged control bits are accessible. this allows the bootstrap mode to be used for self test of the device. a.8 memory map the mc68hc705l16 contains a 16,384-byte eprom, 496 bytes of bootstrap rom, and 512 bytes of ram. an additional 16 bytes of eprom are provided for user vectors at $fff0?$ffff. the mcu?s memory map is shown in figure a-4 . figure a-4. memory map 0000 0015 0016 0063 $0000 $000f $0010 $003f ram 512 bytes i/o registers i/o i/o 64 bytes $0000 $003f $0040 $00c0 $00ff $023f $0240 $0fff $1000 $4fff $5000 $fdff $fe00 $ffdf $ffe0 $ffef $fff0 $ffff unused eprom unused bootstrap rom test vectors user vectors dual-mapped 16 bytes 0 63 64 191 192 255 256 575 576 4095 4096 20479 20480 65023 65024 65503 65504 65519 65520 65535 stack 64 bytes 48 bytes 16 kbytes 496 bytes boot rom mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 137 a.9 boot rom boot rom is 496 bytes of mask rom positioned at $f e00?$ffef. this rom contains bootstrap loader programs and reset/interrupt vectors in the bootstrap mode. the bootstrap loader programs include: eprom programming and verification dumping eprom contents loading programs into the internal ram executing programs in the internal ram a.10 eprom the 16-kbyte eprom is positioned at $1000?$4fff, and the additional 16 bytes of eprom are located at $fff0?$ffff for user vectors. the erased state of eprom is read as $ff and eprom power is supplied from the v pp pin and the v dd pin. the program control register (pcr) is provided fo r eprom programming and testing. the functions of eprom depend on the device mode. in user mode, elat and pgm bits in the pcr are av ailable for user programming, and the remaining test bits become read-only bits. the v pp pin should be tied to 5 volts or programming voltage. a.10.1 programming sequence to program the mc68hc705l16, execute this sequence: set the elat bit write the data to the address to be programmed set the pgm bit delay for an appropriate amount of time clear the pgm bit and the elat bit clearing the pgm bit and the elat bit may be done on a single cpu write. note it is important to remember that an external programming voltage must be applied to the v pp pin while programming, but it should be equal to v dd during normal operations. mc68hc705l16 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 138 freescale semiconductor a.10.2 program control register a program control register is provided for eprom programming. bits 7?3 ? reserved these bits are reserved and read as logic 0 in user mode. bit 2 ? reserved this bit is not used and always reads as logic 0. elat ? eprom latch control 0 = eprom address and data bus configured for normal reads 1 = eprom address and data bus configured fo r programming (writes to eprom cause address and data to be latched.) eprom is in programming mode and cannot be read if elat is logic 1. this bit should not be set when no programming voltage is applied to the v pp pin. pgm ? eprom program command 0 = programming power switched off from eprom array 1 = programming power switched on to eprom array if elat 1, then pgm = 0. address: $000d bit 7654321bit 0 read: rrrrrrelatpgm write: reset:00000000 r= reserved figure a-5. program control register (pcr) lcd 1/2 duty and 1/2 bias timing diagram mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 139 a.11 lcd 1/2 duty and 1/2 bias timing diagram figure a-6. cd 1/2 duty and 1/2 bias timing diagram 1frame duty = 1/2 bias = 1/2 (vlcd1 = vlcd2 = v dd ?vlcd/2, vlcd3 = v dd ?vlcd) bp0 fpx (xx10) bp0?fpx (off) v dd vlcd1, 2 v dd vlcd1, 2 v dd vlcd1, 2 vlcd3 +vlcd +vlcd/2 bp0?fpy (off) bp1?fpy (off) +vlcd/2 0 ?vlcd +vlcd +vlcd/2 0 ?vlcd/2 ?vlcd +vlcd +vlcd/2 vlcd3 vlcd3 0 ?vlcd/2 +vlcd ?vlcd/2 0 ?vlcd/2 ?vlcd bp1 bp1?fpx (on) ?vlcd fpy (xx00) v dd vlcd1, 2 vlcd3 mc68hc705l16 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 140 freescale semiconductor a.12 electrical specifications this section contains parametric and timing information for the mc68hc705l16. a.12.1 maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in this table. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note this device is not guaranteed to operate properly at the maximum ratings. refer to a.13.2 5.0-volt dc electrical characteristics and a.13.3 3.3-volt dc electrical characteristics for guaranteed operating conditions. rating symbol value unit supply voltage v dd v lcd1 v lcd2 v lcd3 ?0.3 to +7.0 v ss ?0.3 to v dd +0.3 v ss ?0.3 to v dd +0.3 v ss ?0.3 to v dd +0.3 v input voltage v in v ss ?0.3 to v dd + 0.3 v bootstrap mode (irq1 pin only) v in v ss ?0.3 to 2 x v dd + 0.3 v output voltage v out v ss ?0.3 to v dd + 0.3 v current drain per pin excluding v dd and v ss i12.5ma operating junction temperature t j +150 c storage temperature range t stg ?55 to +150 c recommended operating conditions mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 141 a.12.2 operating temperature range a.12.3 thermal characteristics a.13 recommended operating conditions a.13.1 eprom pr ogramming voltage characteristic symbol value unit operating temperature range mc68hc705l16 (standard) mc68hc705l16c (extended) t a t l to t h 0 to +70 ?40 to +85 c characteristic symbol value unit thermal resistance 80-pin plastic quad flat pack ja 120 c/w rating (1) 1. +3.0 v dd +5.5 vdc, v ss = 0 vdc, t l t a t h , unless otherwise noted symbol min typ max unit supply voltage (f op = 2.1 mhz) v dd 4.5 5.0 5.5 v (f op = 1.0 mhz) v dd 3.0 ? 5.5 v v lcd1 v dd ? 1/3 v lcd v v lcd2 v dd ? 2/3 v lcd v v lcd3 v dd ? 3/3 v lcd v fast clock oscillation frequency f osc ? 3.52 4.2 mhz external capacitance (f osc = 3.52 mhz) c1 c2 ? ? 33 33 ? ? pf slow clock oscillation frequency f xosc ? 32.768 ? mhz external capacitance (f xosc = 32.768 khz) cx1 cx2 ? ? 18 22 ? ? pf characteristics (1) 1. v dd = 5.0 vdc, v ss = 0 vdc, t a = 25 o c symbol min typ max unit eprom programming voltage v pp 12.0 12.5 13.0 v mc68hc705l16 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 142 freescale semiconductor a.13.2 5.0-volt dc el ectrical characteristics characteristic (1) 1. +4.5 v dd +5.5 vdc, v ss = 0 vdc, t l t a t h , unless otherwise noted. all values shown reflect average measurements. typical values at midpoint of voltage range, 25 c only. symbol min typ max unit output voltage i load = 10.0 a i load = ?10.0 a v ol v oh ? v dd ?0.1 ? ? 0.1 ? v output high voltage (v dd = 5.0 v) (i load = ?0.4 ma) pa0?pa7, pc0?pc5, pd1?pd7, pe0?pe7 v oh v dd ?0.8 ??v output low voltage (v dd = 5.0 v) (i load = 0.8 ma) pa0?pa7, pc0?pc7, pd1?pd7, pe0?pe7 v ol ??0.4v input high voltage pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 v ih 0.8 x v dd ? v dd v input low voltage pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 v il v ss ? 0.2 x v dd v supply current (2), (3), (4), (5) run (f op = 2.1 mhz) wait (f op = 2.1 mhz) stop no clock xosc = 32.768 khz, v dd = 5.0 v, t a = +25 o c 2. run (operating) i dd , wait i dd ; measured using external square wave clock source (f osc = 4.2 mhz); all inputs 0.2 v from rail (v ss or v dd ); no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 3. wait, atop i dd ; all ports configured as inputs; v il = 0.2 v; v ih = v dd ?0.2 v 4. stop i dd measured with osc1 = v ss . 5. wait i dd is affected linearly by the osc2 capacitance. i dd ? ? ? ? 6.0 3.0 3.0 17.0 12.0 6.0 10.0 ? ma ma a a input current (6) (with pullups disabled) pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 6. input current measured with out put transistor turned off and v in = 0 v. i in ?? 1.0 a input current (6) (with pullups enabled, v dd = 5.0 v) pa 0 ? pa 7 pb0?pb7 pc0?pc7 i in 40 40 160 150 150 500 340 340 1000 a a a lcd pin output impedance fp0?fp26 bp0?bp3 zo, fp zo, bp ? ? 10 5 20 18 k ? k ? recommended operating conditions mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 freescale semiconductor 143 a.13.3 3.3-volt dc el ectrical characteristics characteristic (1) 1. +3.0 v dd < +4.5 vdc, v ss = 0 vdc, t l t a t h , unless otherwise noted. all values shown reflect average measurements. typical values at midpoint of voltage range, 25 c only. symbol min typ max unit output voltage i load = 10.0 a i load = ?10.0 a v ol v oh ? v dd ?0.1 ? ? 0.1 ? v output high voltage (v dd = 3.5 v) (i load = ?0.4 ma) pa0?pa7, pc0?pc5, pd1?pd7, pe0?pe7 v oh v dd ?0.8 ??v output low voltage (v dd = 3.5 v) (i load = 0.8 ma) pa0?pa7, pc0?pc7, pd1?pd7, pe0?pe7 v ol ??0.4v input high voltage pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 v ih 0.8 x v dd ? v dd v input low voltage pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 v il v ss ? 0.2 x v dd v supply current (2), (3), (4), (5) run (f op = 1.0 mhz) wait (f op = 1.0 mhz) stop no clock xosc = 32.768 khz, v dd = 3.0 v, t a = +25 o c 2. run (operating) i dd , wait i dd ; measured using external square wave clock source (f osc = 2.0 mhz); all inputs 0.2 v from rail (v ss or v dd ); no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 3. wait, stop i dd ; all ports configured as inputs; v il = 0.2 v; v ih = v dd ?0.2 v 4. stop i dd measured with osc1 = v ss . 5. wait i dd is affected linearly by the osc2 capacitance. i dd ? ? ? ? 1.8 0.8 2.0 8.0 8.0 5.0 10.0 ? ma ma a a input current (6) (with pullups disabled) pa0?pa7, pb0?pb7, pc0?pc7, reset , osc1, xosc1 6. input current measur ed with output transistor turned off and v in = 0 v. i in ?? 1.0 a input current (6) (with pullups enabled, v dd = 3.3 v) pa 0 ? pa 7 pb0?pb7 pc0?pc7 i in 20 20 60 80 80 300 230 230 760 a a a lcd pin output impedance fp0?fp26 bp0?bp3 zo, fp zo, bp ? ? 10 5 20 18 k ? k ? mc68hc705l16 mc68hc05l16 mc68hc705l16 data sheet, rev. 4.1 144 freescale semiconductor a.13.4 3.3-volt and 5. 0-volt control timing a.14 mc order numbers table a-4 shows the mc order numbers for the available package types. characteristic (1) 1. +3.0 v dd +5.5 vdc, v ss = 0 vdc,t l t a t h , unless otherwise noted. symbol min max unit frequency of oscillation (osc) crystal external clock f osc ? dc 4.2 4.2 mhz internal operating frequency (2) , crystal or external clock (f osc /2) v dd = 4.5 v to 5.5 v v dd = 3.0 v to 5.5 v 2. the system clock divider conf iguration (sys1?sys0 bits ) should be selected such that the inte rnal operating frequency (f op ) does not exceed value specified in f op for a given f osc . f op ? ? 2.1 1.0 mhz cycle time (fast osc selected) v dd = 4.5 v to 5.5 v v dd = 3.0 v to 5.5 v t cyc 480 1.0 ? ? ns s reset pulse width (when bus clock active) t rl 1.5 ? t cyc timer resolution input capture (tcap) pulse width t resl t th , t tl 4.0 284 ? ? t cyc ns interrupt pulse width low (edge-triggered) t ilih 284 ? ns interrupt pulse period (3) 3. the minimum period, t ilil , should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . t ilil see note ? t cyc osc1 pulse width (external clock input) t oh , t ol 110 ? ns table a-4. mc order numbers package type operating temperature range mc order number 80-pin plastic quad flat pack (qfp) 0 c to +70 c mc68hc705l16fu ?40 c to +85 c mc68hc705l16cfu blank how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved. mc68hc05l16 rev. 4.1, 9/2005 |
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